Lines Matching refs:wil
75 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
77 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
81 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil)
83 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS),
87 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
89 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
93 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil)
95 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS),
99 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
101 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
104 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
108 void wil6210_mask_halp(struct wil6210_priv *wil)
110 wil_dbg_irq(wil, "mask_halp\n");
112 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
116 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
118 wil_dbg_irq(wil, "mask_irq_pseudo\n");
120 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
122 clear_bit(wil_status_irqen, wil->status);
125 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
127 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
131 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil)
133 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC),
137 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0;
141 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
145 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil)
147 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC),
151 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
153 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
156 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
160 static void wil6210_unmask_halp(struct wil6210_priv *wil)
162 wil_dbg_irq(wil, "unmask_halp\n");
164 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
168 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
170 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
172 set_bit(wil_status_irqen, wil->status);
174 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
177 void wil_mask_irq(struct wil6210_priv *wil)
179 wil_dbg_irq(wil, "mask_irq\n");
181 wil6210_mask_irq_tx(wil);
182 wil6210_mask_irq_tx_edma(wil);
183 wil6210_mask_irq_rx(wil);
184 wil6210_mask_irq_rx_edma(wil);
185 wil6210_mask_irq_misc(wil, true);
186 wil6210_mask_irq_pseudo(wil);
189 void wil_unmask_irq(struct wil6210_priv *wil)
191 wil_dbg_irq(wil, "unmask_irq\n");
193 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
195 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
197 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
199 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),
201 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),
204 wil6210_unmask_irq_pseudo(wil);
205 if (wil->use_enhanced_dma_hw) {
206 wil6210_unmask_irq_tx_edma(wil);
207 wil6210_unmask_irq_rx_edma(wil);
209 wil6210_unmask_irq_tx(wil);
210 wil6210_unmask_irq_rx(wil);
212 wil6210_unmask_irq_misc(wil, true);
215 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil)
219 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC);
221 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES);
224 moderation = wil->rx_max_burst_duration |
226 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation);
227 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation);
232 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE);
233 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1);
236 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
238 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr;
240 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
249 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
250 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
251 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
252 wil->tx_max_burst_duration);
254 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
258 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
259 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
260 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
261 wil->tx_interframe_timeout);
263 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
267 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
268 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
269 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
270 wil->rx_max_burst_duration);
272 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
276 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
277 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
278 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
279 wil->rx_interframe_timeout);
281 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
287 struct wil6210_priv *wil = cookie;
291 wil6210_mask_irq_rx(wil);
293 isr = wil_ioread32_and_clear(wil->csr +
298 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
301 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
302 wil6210_unmask_irq_rx(wil);
314 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
319 if (likely(test_bit(wil_status_fwready, wil->status))) {
320 if (likely(test_bit(wil_status_napi_en, wil->status))) {
321 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
323 napi_schedule(&wil->napi_rx);
326 wil,
330 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
335 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
339 atomic_inc(&wil->isr_count_rx);
342 wil6210_unmask_irq_rx(wil);
349 struct wil6210_priv *wil = cookie;
353 wil6210_mask_irq_rx_edma(wil);
355 isr = wil_ioread32_and_clear(wil->csr +
360 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
363 wil_err(wil, "spurious IRQ: RX\n");
364 wil6210_unmask_irq_rx_edma(wil);
369 wil_dbg_irq(wil, "RX status ring\n");
371 if (likely(test_bit(wil_status_fwready, wil->status))) {
372 if (likely(test_bit(wil_status_napi_en, wil->status))) {
373 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
375 napi_schedule(&wil->napi_rx);
377 wil_err(wil,
381 wil_err(wil, "Got Rx interrupt while in reset\n");
386 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
390 atomic_inc(&wil->isr_count_rx);
393 wil6210_unmask_irq_rx_edma(wil);
400 struct wil6210_priv *wil = cookie;
404 wil6210_mask_irq_tx_edma(wil);
406 isr = wil_ioread32_and_clear(wil->csr +
411 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
414 wil_err(wil, "spurious IRQ: TX\n");
415 wil6210_unmask_irq_tx_edma(wil);
420 wil_dbg_irq(wil, "TX status ring\n");
422 if (likely(test_bit(wil_status_fwready, wil->status))) {
423 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
425 napi_schedule(&wil->napi_tx);
427 wil_err(wil, "Got Tx status ring IRQ while in reset\n");
432 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
436 atomic_inc(&wil->isr_count_tx);
439 wil6210_unmask_irq_tx_edma(wil);
446 struct wil6210_priv *wil = cookie;
450 wil6210_mask_irq_tx(wil);
452 isr = wil_ioread32_and_clear(wil->csr +
457 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
460 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
461 wil6210_unmask_irq_tx(wil);
466 wil_dbg_irq(wil, "TX done\n");
470 if (likely(test_bit(wil_status_fwready, wil->status))) {
471 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
473 napi_schedule(&wil->napi_tx);
475 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
480 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
485 atomic_inc(&wil->isr_count_tx);
488 wil6210_unmask_irq_tx(wil);
493 static void wil_notify_fw_error(struct wil6210_priv *wil)
495 struct device *dev = &wil->main_ndev->dev;
501 wil_err(wil, "Notify about firmware error\n");
505 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
508 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
510 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
511 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
514 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
519 if (wil->mbox_ctl.rx.entry_size < min_size) {
520 wil_err(wil, "rx mbox entry too small (%d)\n",
521 wil->mbox_ctl.rx.entry_size);
524 if (wil->mbox_ctl.tx.entry_size < min_size) {
525 wil_err(wil, "tx mbox entry too small (%d)\n",
526 wil->mbox_ctl.tx.entry_size);
535 struct wil6210_priv *wil = cookie;
538 wil6210_mask_irq_misc(wil, false);
540 isr = wil_ioread32_and_clear(wil->csr +
545 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
548 wil_err(wil, "spurious IRQ: MISC\n");
549 wil6210_unmask_irq_misc(wil, false);
554 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr);
556 wil_r(wil, wil->rgf_ucode_assert_code_addr);
558 wil_err(wil,
561 clear_bit(wil_status_fwready, wil->status);
570 wil_dbg_irq(wil, "IRQ: FW ready\n");
571 wil_cache_mbox_regs(wil);
572 if (wil_validate_mbox_regs(wil))
573 set_bit(wil_status_mbox_ready, wil->status);
583 if (wil->halp.handle_icr) {
585 wil->halp.handle_icr = false;
586 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
587 wil6210_mask_irq_misc(wil, true);
588 complete(&wil->halp.comp);
592 wil->isr_misc = isr;
597 wil6210_unmask_irq_misc(wil, false);
604 struct wil6210_priv *wil = cookie;
605 u32 isr = wil->isr_misc;
608 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
611 wil->recovery_state = fw_recovery_pending;
612 wil_fw_core_dump(wil);
613 wil_notify_fw_error(wil);
615 if (wil->platform_ops.notify) {
616 wil_err(wil, "notify platform driver about FW crash");
617 wil->platform_ops.notify(wil->platform_handle,
620 wil_fw_error_recovery(wil);
624 wil_dbg_irq(wil, "MBOX event\n");
625 wmi_recv_cmd(wil);
630 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
632 wil->isr_misc = 0;
634 wil6210_unmask_irq_misc(wil, false);
639 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) {
640 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
641 wil->suspend_resp_comp = true;
642 wake_up_interruptible(&wil->wq);
651 struct wil6210_priv *wil = cookie;
653 wil_dbg_irq(wil, "Thread IRQ\n");
655 if (wil->isr_misc)
658 wil6210_unmask_irq_pseudo(wil);
660 if (wil->suspend_resp_rcvd) {
661 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
662 wil->suspend_resp_comp = true;
663 wake_up_interruptible(&wil->wq);
675 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
681 if (!test_bit(wil_status_irqen, wil->status)) {
682 if (wil->use_enhanced_dma_hw) {
683 icm_rx = wil_ioread32_and_clear(wil->csr +
686 icr_rx = wil_ioread32_and_clear(wil->csr +
689 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR +
691 icm_tx = wil_ioread32_and_clear(wil->csr +
694 icr_tx = wil_ioread32_and_clear(wil->csr +
697 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR +
700 icm_rx = wil_ioread32_and_clear(wil->csr +
703 icr_rx = wil_ioread32_and_clear(wil->csr +
706 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
708 icm_tx = wil_ioread32_and_clear(wil->csr +
711 icr_tx = wil_ioread32_and_clear(wil->csr +
714 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
717 icm_misc = wil_ioread32_and_clear(wil->csr +
720 icr_misc = wil_ioread32_and_clear(wil->csr +
723 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
732 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
750 struct wil6210_priv *wil = cookie;
751 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
760 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
764 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
766 wil6210_mask_irq_pseudo(wil);
782 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
786 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
795 wil6210_unmask_irq_pseudo(wil);
800 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
809 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED,
810 WIL_NAME "_tx", wil);
814 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED,
815 WIL_NAME "_rx", wil);
821 IRQF_SHARED, WIL_NAME "_misc", wil);
827 free_irq(irq + 1, wil);
829 free_irq(irq, wil);
842 void wil6210_clear_irq(struct wil6210_priv *wil)
844 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
846 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
848 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) +
850 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) +
852 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
857 void wil6210_set_halp(struct wil6210_priv *wil)
859 wil_dbg_irq(wil, "set_halp\n");
861 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
865 void wil6210_clear_halp(struct wil6210_priv *wil)
867 wil_dbg_irq(wil, "clear_halp\n");
869 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
871 wil6210_unmask_halp(wil);
874 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
878 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n",
879 wil->n_msi ? "MSI" : "INTx", wil->n_msi);
881 if (wil->use_enhanced_dma_hw) {
882 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma;
883 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma;
885 wil->txrx_ops.irq_tx = wil6210_irq_tx;
886 wil->txrx_ops.irq_rx = wil6210_irq_rx;
889 if (wil->n_msi == 3)
890 rc = wil6210_request_3msi(wil, irq);
894 wil->n_msi ? 0 : IRQF_SHARED,
895 WIL_NAME, wil);
899 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
901 wil_dbg_misc(wil, "fini_irq:\n");
903 wil_mask_irq(wil);
904 free_irq(irq, wil);
905 if (wil->n_msi == 3) {
906 free_irq(irq + 1, wil);
907 free_irq(irq + 2, wil);