Lines Matching refs:wcn
30 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data)
36 writel(data, wcn->ccu_base + addr);
39 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
45 writel(data, wcn->dxe_base + addr);
48 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
50 *data = readl(wcn->dxe_base + addr);
101 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn)
105 wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L;
106 wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H;
107 wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L;
108 wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H;
110 wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L;
111 wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H;
112 wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L;
113 wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H;
115 wcn->dxe_tx_l_ch.dxe_wq = WCN36XX_DXE_WQ_TX_L;
116 wcn->dxe_tx_h_ch.dxe_wq = WCN36XX_DXE_WQ_TX_H;
118 wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD;
119 wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD;
121 wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB;
122 wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB;
124 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L;
125 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H;
127 wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L;
128 wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H;
131 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch);
134 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch);
137 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch);
140 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch);
145 ret = qcom_smem_state_update_bits(wcn->tx_enable_state,
156 wcn36xx_dxe_free_ctl_blks(wcn);
160 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn)
162 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch);
163 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch);
164 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch);
165 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch);
259 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
263 wcn36xx_dxe_read_register(wcn,
269 wcn36xx_dxe_write_register(wcn,
275 static void wcn36xx_dxe_disable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
279 wcn36xx_dxe_read_register(wcn,
285 wcn36xx_dxe_write_register(wcn,
315 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,
324 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL);
331 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
343 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status)
349 spin_lock_irqsave(&wcn->dxe_lock, flags);
350 skb = wcn->tx_ack_skb;
351 wcn->tx_ack_skb = NULL;
352 del_timer(&wcn->tx_ack_timer);
353 spin_unlock_irqrestore(&wcn->dxe_lock, flags);
369 ieee80211_tx_status_irqsafe(wcn->hw, skb);
370 ieee80211_wake_queues(wcn->hw);
375 struct wcn36xx *wcn = from_timer(wcn, t, tx_ack_timer);
383 spin_lock_irqsave(&wcn->dxe_lock, flags);
384 skb = wcn->tx_ack_skb;
385 wcn->tx_ack_skb = NULL;
386 spin_unlock_irqrestore(&wcn->dxe_lock, flags);
395 ieee80211_tx_status_irqsafe(wcn->hw, skb);
396 ieee80211_wake_queues(wcn->hw);
399 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
418 dma_unmap_single(wcn->dev, ctl->desc->src_addr_l,
424 ieee80211_tx_status_irqsafe(wcn->hw, ctl->skb);
427 spin_lock(&wcn->dxe_lock);
428 if (WARN_ON(wcn->tx_ack_skb))
429 ieee80211_free_txskb(wcn->hw, wcn->tx_ack_skb);
430 wcn->tx_ack_skb = ctl->skb; /* Tracking ref */
431 mod_timer(&wcn->tx_ack_timer, jiffies + HZ / 10);
432 spin_unlock(&wcn->dxe_lock);
436 ieee80211_free_txskb(wcn->hw, ctl->skb);
439 if (wcn->queues_stopped) {
440 wcn->queues_stopped = false;
441 ieee80211_wake_queues(wcn->hw);
455 struct wcn36xx *wcn = (struct wcn36xx *)dev;
458 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
461 wcn36xx_dxe_read_register(wcn,
465 wcn36xx_dxe_write_register(wcn,
470 wcn36xx_dxe_write_register(wcn,
479 wcn36xx_dxe_write_register(wcn,
485 wcn36xx_dxe_write_register(wcn,
495 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
500 wcn36xx_dxe_read_register(wcn,
504 wcn36xx_dxe_write_register(wcn,
509 wcn36xx_dxe_write_register(wcn,
518 wcn36xx_dxe_write_register(wcn,
524 wcn36xx_dxe_write_register(wcn,
534 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
543 struct wcn36xx *wcn = (struct wcn36xx *)dev;
545 wcn36xx_dxe_rx_frame(wcn);
550 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
554 ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete,
555 IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn);
561 ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH,
562 "wcn36xx_rx", wcn);
568 enable_irq_wake(wcn->rx_irq);
573 free_irq(wcn->tx_irq, wcn);
579 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
593 wcn36xx_dxe_read_register(wcn, status_reg, &int_reason);
594 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, int_mask);
597 wcn36xx_dxe_write_register(wcn,
605 wcn36xx_dxe_write_register(wcn,
610 wcn36xx_dxe_write_register(wcn,
630 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC);
635 dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE,
637 wcn36xx_rx_skb(wcn, skb);
650 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, en_mask);
659 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn)
663 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
667 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_l_ch,
675 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_h_ch,
685 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn)
693 wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
696 s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H;
697 cpu_addr = dma_alloc_coherent(wcn->dev, s,
698 &wcn->mgmt_mem_pool.phy_addr,
703 wcn->mgmt_mem_pool.virt_addr = cpu_addr;
708 wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
711 s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L;
712 cpu_addr = dma_alloc_coherent(wcn->dev, s,
713 &wcn->data_mem_pool.phy_addr,
718 wcn->data_mem_pool.virt_addr = cpu_addr;
723 wcn36xx_dxe_free_mem_pools(wcn);
728 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn)
730 if (wcn->mgmt_mem_pool.virt_addr)
731 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size *
733 wcn->mgmt_mem_pool.virt_addr,
734 wcn->mgmt_mem_pool.phy_addr);
736 if (wcn->data_mem_pool.virt_addr) {
737 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size *
739 wcn->data_mem_pool.virt_addr,
740 wcn->data_mem_pool.phy_addr);
744 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
756 ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
768 ieee80211_stop_queues(wcn->hw);
769 wcn->queues_stopped = true;
801 desc_skb->src_addr_l = dma_map_single(wcn->dev,
805 if (dma_mapping_error(wcn->dev, desc_skb->src_addr_l)) {
806 dev_err(wcn->dev, "unable to DMA map src_addr_l\n");
835 qcom_smem_state_update_bits(wcn->tx_rings_empty_state,
842 wcn36xx_dxe_write_register(wcn,
852 int wcn36xx_dxe_init(struct wcn36xx *wcn)
857 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);
862 if (wcn->is_pronto)
863 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data);
865 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data);
870 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_l_ch);
872 dev_err(wcn->dev, "Error allocating descriptor\n");
875 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool);
878 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,
879 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr);
882 wcn36xx_dxe_write_register(wcn,
886 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data);
891 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_h_ch);
893 dev_err(wcn->dev, "Error allocating descriptor\n");
897 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool);
900 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,
901 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr);
904 wcn36xx_dxe_write_register(wcn,
908 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data);
913 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_l_ch);
915 dev_err(wcn->dev, "Error allocating descriptor\n");
920 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch);
923 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,
924 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr);
927 wcn36xx_dxe_write_register(wcn,
932 wcn36xx_dxe_write_register(wcn,
934 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l);
937 wcn36xx_dxe_write_register(wcn,
944 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_h_ch);
946 dev_err(wcn->dev, "Error allocating descriptor\n");
951 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch);
954 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,
955 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr);
958 wcn36xx_dxe_write_register(wcn,
963 wcn36xx_dxe_write_register(wcn,
965 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l);
968 wcn36xx_dxe_write_register(wcn,
972 ret = wcn36xx_dxe_request_irqs(wcn);
976 timer_setup(&wcn->tx_ack_timer, wcn36xx_dxe_tx_timer, 0);
979 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);
980 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);
981 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);
982 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);
987 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);
989 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);
991 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);
993 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);
998 void wcn36xx_dxe_deinit(struct wcn36xx *wcn)
1003 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);
1004 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);
1005 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);
1006 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);
1008 free_irq(wcn->tx_irq, wcn);
1009 free_irq(wcn->rx_irq, wcn);
1010 del_timer(&wcn->tx_ack_timer);
1012 if (wcn->tx_ack_skb) {
1013 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb);
1014 wcn->tx_ack_skb = NULL;
1019 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);
1021 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch);
1022 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch);
1024 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);
1025 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);
1026 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);
1027 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);