Lines Matching refs:set
605 * Read back AR_WA into a permanent copy and set bits 14 and 17.
1201 * set AHB_MODE not to do cacheline prefetches
1247 * So set the usable tx buf size also to half to
1270 u32 set = AR_STA_ID1_KSRCH_MODE;
1276 set |= AR_STA_ID1_ADHOC;
1284 set |= AR_STA_ID1_STA_AP;
1291 set = 0;
1294 REG_RMW(ah, AR_STA_ID1, set, mask);
1589 ath_err(common, "Failed to set channel\n");
2081 /* set HW specific DFS configuration */
2136 * frames. If request, set power mode of chip to
2727 /* BSP should set the corresponding MUX register correctly.
3058 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3060 if (set)