Lines Matching defs:pCap
1547 struct ath9k_hw_capabilities *pCap = &ah->caps;
1553 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1791 struct ath9k_hw_capabilities *pCap = &ah->caps;
1813 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2141 struct ath9k_hw_capabilities *pCap = &ah->caps;
2145 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2327 struct ath9k_hw_capabilities *pCap = &ah->caps;
2369 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2433 struct ath9k_hw_capabilities *pCap = &ah->caps;
2436 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2437 pCap->gpio_mask = AR9271_GPIO_MASK;
2439 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2440 pCap->gpio_mask = AR7010_GPIO_MASK;
2442 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2443 pCap->gpio_mask = AR9287_GPIO_MASK;
2445 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2446 pCap->gpio_mask = AR9285_GPIO_MASK;
2448 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2449 pCap->gpio_mask = AR9280_GPIO_MASK;
2451 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2452 pCap->gpio_mask = AR9300_GPIO_MASK;
2454 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2455 pCap->gpio_mask = AR9330_GPIO_MASK;
2457 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2458 pCap->gpio_mask = AR9340_GPIO_MASK;
2460 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2461 pCap->gpio_mask = AR9462_GPIO_MASK;
2463 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2464 pCap->gpio_mask = AR9485_GPIO_MASK;
2466 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2467 pCap->gpio_mask = AR9531_GPIO_MASK;
2469 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2470 pCap->gpio_mask = AR9550_GPIO_MASK;
2472 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2473 pCap->gpio_mask = AR9561_GPIO_MASK;
2475 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2476 pCap->gpio_mask = AR9565_GPIO_MASK;
2478 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2479 pCap->gpio_mask = AR9580_GPIO_MASK;
2481 pCap->num_gpio_pins = AR_NUM_GPIO;
2482 pCap->gpio_mask = AR_GPIO_MASK;
2488 struct ath9k_hw_capabilities *pCap = &ah->caps;
2515 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2522 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2525 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2536 pCap->chip_chainmask = 1;
2538 pCap->chip_chainmask = 7;
2543 pCap->chip_chainmask = 3;
2545 pCap->chip_chainmask = 7;
2547 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2556 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2558 pCap->rx_chainmask = 0x7;
2561 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2563 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2564 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2565 ah->txchainmask = pCap->tx_chainmask;
2566 ah->rxchainmask = pCap->rx_chainmask;
2577 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2579 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2582 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2584 pCap->rts_aggr_limit = (8 * 1024);
2594 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2598 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2600 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2603 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2605 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2608 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2611 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2613 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2614 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2615 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2616 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2617 pCap->txs_len = sizeof(struct ar9003_txs);
2619 pCap->tx_desc_len = sizeof(struct ath_desc);
2621 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2625 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2633 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2640 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2648 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2654 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2660 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2662 tx_chainmask = pCap->tx_chainmask;
2663 rx_chainmask = pCap->rx_chainmask;
2666 pCap->max_txchains++;
2668 pCap->max_rxchains++;
2676 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2679 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2684 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;