Lines Matching defs:clock
43 * that don't fit on other places such as clock, sleep and power control
91 * ath5k_hw_htoclock() - Translate usec to hw clock units
95 * Translate usecs to hw clock units based on the current
96 * hw clock rate.
98 * Returns number of clock units
108 * ath5k_hw_clocktoh() - Translate hw clock units to usec
110 * @clock: value in hw clock units
112 * Translate hw clock units to usecs based on the current
113 * hw clock rate.
118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
121 return clock / common->clockrate;
125 * ath5k_hw_init_core_clock() - Initialize core clock
128 * Initialize core clock parameters (usec, usec32, latencies etc),
136 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
139 * Set core clock frequency
143 clock = 40;
146 clock = 22;
150 clock = 44;
154 /* Use clock multiplier for non-default
158 clock *= 2;
161 clock /= 2;
164 clock /= 4;
170 common->clockrate = clock;
176 usec = clock - 1;
183 clock);
191 /* Remain on 40MHz clock ? */
268 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
270 * @enable: Enable sleep clock operation (false to disable)
273 * as ref. clock instead of 32/40MHz clock and baseband clocks
328 /* Enable sleep clock operation */
334 /* Disable sleep clock operation and
672 u32 turbo, mode, clock, bus_flags;
677 clock = 0;
749 clock = AR5K_PHY_PLL_RF5112;
752 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
757 clock |= AR5K_PHY_PLL_44MHZ;
780 clock = AR5K_PHY_PLL_40MHZ_5413;
782 clock |= AR5K_PHY_PLL_40MHZ;
801 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
818 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
819 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
917 /* Clear QCU/DCU clock gating register */
1166 /* Disable sleep clock operation
1290 /* Initialize core clock settings */
1362 * Enable 32KHz clock function for AR5212+ chips