Lines Matching defs:queue
35 * basically we have 10 queues to play with. Each queue has a matching
36 * QCU that controls when the queue will get triggered and multiple QCUs
39 * and DCUs allowing us to have different DFS settings for each queue.
41 * When a frame goes into a TX queue, QCU decides when it'll trigger a
43 * it's buffer or -if it's a beacon queue- if it's time to fire up the queue
58 * ath5k_hw_num_tx_pending() - Get number of pending frames for a given queue
60 * @queue: One of enum ath5k_tx_queue_id
63 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
66 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
68 /* Return if queue is declared inactive */
69 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
76 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
82 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
89 * ath5k_hw_release_tx_queue() - Set a transmit queue inactive
91 * @queue: One of enum ath5k_tx_queue_id
94 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
96 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
99 /* This queue will be skipped in further operations */
100 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
102 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
132 * ath5k_hw_get_tx_queueprops() - Get properties for a transmit queue
134 * @queue: One of enum ath5k_tx_queue_id
138 ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
141 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
146 * ath5k_hw_set_tx_queueprops() - Set properties for a transmit queue
148 * @queue: One of enum ath5k_tx_queue_id
151 * Returns 0 on success or -EIO if queue is inactive
154 ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
159 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
161 qi = &ah->ah_txq[queue];
195 * ath5k_hw_setup_tx_queue() - Initialize a transmit queue
206 unsigned int queue;
210 * Get queue by type
216 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
220 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
228 queue = queue_info->tqi_subtype;
231 queue = AR5K_TX_QUEUE_ID_UAPSD;
234 queue = AR5K_TX_QUEUE_ID_BEACON;
237 queue = AR5K_TX_QUEUE_ID_CAB;
245 * Setup internal queue structure
247 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
248 ah->ah_txq[queue].tqi_type = queue_type;
252 ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);
262 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
264 return queue;
275 * @queue: One of enum ath5k_tx_queue_id
277 * This function is used when initializing a queue, to set
282 unsigned int queue)
284 /* Single data queue on AR5210 */
286 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
288 if (queue > 0)
311 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
316 * ath5k_hw_reset_tx_queue() - Initialize a single hw queue
318 * @queue: One of enum ath5k_tx_queue_id
320 * Set DCF properties for the given transmit queue on DCU
321 * and configures all queue-specific parameters.
324 ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
326 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
328 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
330 /* Skip if queue inactive or if we are on AR5210
344 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
347 * Set tx retry limits for this queue
349 ath5k_hw_set_tx_retry_limits(ah, queue);
357 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
362 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
371 AR5K_QUEUE_CBRCFG(queue));
373 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
377 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
386 AR5K_QUEUE_RDYTIMECFG(queue));
392 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
395 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
402 AR5K_QUEUE_DFS_MISC(queue));
407 AR5K_QUEUE_DFS_MISC(queue));
410 * Set registers by queue type
414 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
419 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
429 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
439 AR5K_QUEUE_RDYTIMECFG(queue));
441 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
447 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
459 * Enable interrupts for this tx queue
463 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
466 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
469 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
472 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
475 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
478 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
481 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
484 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
487 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
533 /* No queue has TXNOFRM enabled, disable the interrupt
539 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
705 "failed to reset TX queue #%d\n", i);