Lines Matching defs:data0
1261 u32 data0, data1, clock;
1267 data0 = data1 = 0;
1278 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1292 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1294 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1316 u32 data, data0, data1, data2;
1319 data = data0 = data1 = data2 = 0;
1325 * (3040/2). data0 is used to set the PLL divider and data1
1332 data0 = ((2 * (c - 704)) - 3040) / 10;
1338 data0 = ((2 * (c - 672)) - 3040) / 10;
1343 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1346 * and set using data2. LO is at 4800Hz and data0 is again used
1355 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1358 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1361 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1366 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1370 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1390 u32 data, data0, data2;
1393 data = data0 = data2 = 0;
1397 data0 = ath5k_hw_bitswap((c - 2272), 8);
1402 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1404 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1406 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1411 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1415 data = (data0 << 4) | data2 << 2 | 0x1001;