Lines Matching refs:ee
40 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
141 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
144 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
153 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
154 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
157 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
158 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
164 ee->ee_is_hb63 = true;
166 ee->ee_is_hb63 = false;
169 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
170 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
179 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
192 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
205 ee->ee_ant_control[mode][i++] = val & 0x3f;
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
221 ee->ee_ant_control[mode][i++] = val & 0x3f;
225 (ee->ee_ant_control[mode][0] << 4);
227 ee->ee_ant_control[mode][1] |
228 (ee->ee_ant_control[mode][2] << 6) |
229 (ee->ee_ant_control[mode][3] << 12) |
230 (ee->ee_ant_control[mode][4] << 18) |
231 (ee->ee_ant_control[mode][5] << 24);
233 ee->ee_ant_control[mode][6] |
234 (ee->ee_ant_control[mode][7] << 6) |
235 (ee->ee_ant_control[mode][8] << 12) |
236 (ee->ee_ant_control[mode][9] << 18) |
237 (ee->ee_ant_control[mode][10] << 24);
252 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
256 ee->ee_n_piers[mode] = 0;
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
262 ee->ee_db[mode][3] = (val >> 2) & 0x7;
263 ee->ee_ob[mode][2] = (val << 1) & 0x7;
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
267 ee->ee_db[mode][2] = (val >> 12) & 0x7;
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
269 ee->ee_db[mode][1] = (val >> 6) & 0x7;
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
271 ee->ee_db[mode][0] = val & 0x7;
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
276 ee->ee_db[mode][1] = val & 0x7;
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
282 ee->ee_thr_62[mode] = val & 0xff;
285 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
297 ee->ee_noise_floor_thr[mode] = val & 0xff;
300 ee->ee_noise_floor_thr[mode] =
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
306 ee->ee_xpd[mode] = val & 0x1;
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
317 ee->ee_xr_power[mode] = val & 0x3f;
320 ee->ee_ob[mode][0] = val & 0x7;
321 ee->ee_db[mode][0] = (val >> 3) & 0x7;
326 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
327 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
335 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
337 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
359 ee->ee_margin_tx_rx[mode] = val & 0x3f;
364 ee->ee_pwr_cal_b[0].freq =
365 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
366 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
367 ee->ee_n_piers[mode]++;
369 ee->ee_pwr_cal_b[1].freq =
370 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
371 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
372 ee->ee_n_piers[mode]++;
375 ee->ee_pwr_cal_b[2].freq =
376 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
377 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
378 ee->ee_n_piers[mode]++;
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
386 ee->ee_pwr_cal_g[0].freq =
387 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
388 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
389 ee->ee_n_piers[mode]++;
391 ee->ee_pwr_cal_g[1].freq =
392 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
393 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
394 ee->ee_n_piers[mode]++;
397 ee->ee_turbo_max_power[mode] = val & 0x7f;
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
401 ee->ee_pwr_cal_g[2].freq =
402 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
403 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
404 ee->ee_n_piers[mode]++;
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
411 ee->ee_q_cal[mode] = val & 0x1f;
415 ee->ee_cck_ofdm_gain_delta = val & 0xff;
423 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
440 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2)
441 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
469 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
482 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
483 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
501 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
513 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
519 ee->ee_n_piers[mode] = 0;
527 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
529 ee->ee_n_piers[mode]++;
535 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
537 ee->ee_n_piers[mode]++;
550 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
551 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
556 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
588 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
591 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
608 pcal = ee->ee_pwr_cal_b;
611 pcal = ee->ee_pwr_cal_g;
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
675 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
677 chinfo = ee->ee_pwr_cal_a;
680 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
682 chinfo = ee->ee_pwr_cal_b;
685 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
687 chinfo = ee->ee_pwr_cal_g;
693 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
717 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
721 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
724 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
743 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
752 ee->ee_pd_gains[mode] = 1;
798 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
804 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
807 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
816 pcal = ee->ee_pwr_cal_a;
819 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
820 !AR5K_EEPROM_HDR_11G(ee->ee_header))
823 pcal = ee->ee_pwr_cal_b;
830 ee->ee_n_piers[mode] = 3;
833 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
836 pcal = ee->ee_pwr_cal_g;
843 ee->ee_n_piers[mode] = 3;
849 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
908 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
910 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
914 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
928 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1021 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1024 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1037 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1040 ee->ee_pd_gains[mode] = pd_gains;
1050 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1054 gen_chan_info = ee->ee_pwr_cal_a;
1057 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1058 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1062 gen_chan_info = ee->ee_pwr_cal_b;
1065 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1066 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1068 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1072 gen_chan_info = ee->ee_pwr_cal_g;
1078 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1115 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1154 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1159 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1160 sz *= ee->ee_n_piers[mode];
1168 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1170 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1174 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1175 offset += ath5k_pdgains_size_2413(ee,
1180 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1181 offset += ath5k_pdgains_size_2413(ee,
1200 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1202 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1206 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1220 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1228 if (pdg == ee->ee_pd_gains[mode] - 1)
1267 if (pdg == ee->ee_pd_gains[mode] - 1)
1284 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1287 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1300 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1304 ee->ee_pd_gains[mode] = pd_gains;
1309 offset = ath5k_cal_data_offset_2413(ee, mode);
1312 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1317 chinfo = ee->ee_pwr_cal_a;
1320 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1325 chinfo = ee->ee_pwr_cal_b;
1328 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1333 chinfo = ee->ee_pwr_cal_g;
1339 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1475 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1482 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1483 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1486 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1487 rate_pcal_info = ee->ee_rate_tpwr_a;
1488 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN;
1491 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1492 rate_pcal_info = ee->ee_rate_tpwr_b;
1493 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1496 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1497 rate_pcal_info = ee->ee_rate_tpwr_g;
1498 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1505 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1509 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1530 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1570 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1576 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1579 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1612 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1613 offset = AR5K_EEPROM_CTL(ee->ee_version);
1614 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1615 for (i = 0; i < ee->ee_ctls; i += 2) {
1617 ee->ee_ctl[i] = (val >> 8) & 0xff;
1618 ee->ee_ctl[i + 1] = val & 0xff;
1622 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1623 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1626 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1628 rep = ee->ee_ctl_pwr;
1629 for (i = 0; i < ee->ee_ctls; i++) {
1630 switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1639 if (ee->ee_ctl[i] == 0) {
1640 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1647 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1698 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1710 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1715 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1716 AR5K_EEPROM_N_CTLS(ee->ee_version);
1718 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1720 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1722 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1723 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1724 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1725 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1728 ee->ee_spur_chans[i][0] = val;
1731 ee->ee_spur_chans[i][1] = val;