Lines Matching refs:val
307 u32 val;
313 val = ath11k_hif_read32(ab, addr);
314 val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN;
315 val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN,
317 ath11k_hif_write32(ab, addr, val);
324 u32 val;
335 val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR,
340 HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab), val);
349 val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
354 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val);
356 val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) |
358 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val);
361 val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD,
364 val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD,
370 val);
387 val = 0;
389 val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP;
391 val |= HAL_REO1_RING_MISC_HOST_FW_SWAP;
393 val |= HAL_REO1_RING_MISC_MSI_SWAP;
394 val |= HAL_REO1_RING_MISC_SRNG_ENABLE;
396 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val);
403 u32 val;
414 val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR,
420 val);
429 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
434 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
436 val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
437 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
443 val = FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD,
446 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD,
452 val);
454 val = 0;
456 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD,
461 val);
482 val = 0;
484 val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP;
486 val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP;
488 val |= HAL_TCL1_RING_MISC_MSI_SWAP;
491 val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE;
493 val |= HAL_TCL1_RING_MISC_SRNG_ENABLE;
495 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val);