Lines Matching defs:htt
21 #include "htt.h"
3417 lockdep_assert_held(&ar->htt.tx_lock);
3438 lockdep_assert_held(&ar->htt.tx_lock);
3458 lockdep_assert_held(&ar->htt.tx_lock);
3469 lockdep_assert_held(&ar->htt.tx_lock);
3489 lockdep_assert_held(&ar->htt.tx_lock);
3534 spin_lock_bh(&ar->htt.tx_lock);
3539 spin_unlock_bh(&ar->htt.tx_lock);
3574 if (ar->htt.target_version_major < 3 &&
3769 return (ar->htt.target_version_major >= 3 &&
3770 ar->htt.target_version_minor >= 4 &&
3805 else if (ar->htt.target_version_major >= 3)
3819 struct ath10k_htt *htt = &ar->htt;
3824 ret = ath10k_htt_tx(htt, txmode, skb);
3827 ret = ath10k_htt_mgmt_tx(htt, skb);
4095 spin_lock_bh(&ar->htt.tx_lock);
4096 idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {
4101 spin_unlock_bh(&ar->htt.tx_lock);
4134 if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)
4137 if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)
4196 struct ath10k_htt *htt = &ar->htt;
4209 spin_lock_bh(&ar->htt.tx_lock);
4210 ret = ath10k_htt_tx_inc_pending(htt);
4211 spin_unlock_bh(&ar->htt.tx_lock);
4218 spin_lock_bh(&ar->htt.tx_lock);
4219 ath10k_htt_tx_dec_pending(htt);
4220 spin_unlock_bh(&ar->htt.tx_lock);
4237 spin_lock_bh(&ar->htt.tx_lock);
4238 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);
4241 ath10k_htt_tx_dec_pending(htt);
4242 spin_unlock_bh(&ar->htt.tx_lock);
4245 spin_unlock_bh(&ar->htt.tx_lock);
4252 spin_lock_bh(&ar->htt.tx_lock);
4253 ath10k_htt_tx_dec_pending(htt);
4255 ath10k_htt_tx_mgmt_dec_pending(htt);
4256 spin_unlock_bh(&ar->htt.tx_lock);
4261 spin_lock_bh(&ar->htt.tx_lock);
4263 spin_unlock_bh(&ar->htt.tx_lock);
4295 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)
4298 if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))
4481 struct ath10k_htt *htt = &ar->htt;
4505 spin_lock_bh(&ar->htt.tx_lock);
4508 ret = ath10k_htt_tx_inc_pending(htt);
4512 spin_unlock_bh(&ar->htt.tx_lock);
4517 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);
4521 ath10k_htt_tx_dec_pending(htt);
4522 spin_unlock_bh(&ar->htt.tx_lock);
4526 spin_unlock_bh(&ar->htt.tx_lock);
4533 spin_lock_bh(&ar->htt.tx_lock);
4534 ath10k_htt_tx_dec_pending(htt);
4536 ath10k_htt_tx_mgmt_dec_pending(htt);
4537 spin_unlock_bh(&ar->htt.tx_lock);
4551 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)
5704 spin_lock_bh(&ar->htt.tx_lock);
5707 spin_unlock_bh(&ar->htt.tx_lock);
5855 spin_lock_bh(&ar->htt.tx_lock);
5857 spin_unlock_bh(&ar->htt.tx_lock);
7902 time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({
7905 spin_lock_bh(&ar->htt.tx_lock);
7906 empty = (ar->htt.num_pending_tx == 0);
7907 spin_unlock_bh(&ar->htt.tx_lock);
7936 ath10k_htt_flush_tx(&ar->htt);
9175 if (ar->htt.disable_tx_comp) {