Lines Matching refs:plx
75 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
252 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
254 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
300 port->card->plx + PLX_DOORBELL_TO_CARD);
395 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
437 port->card->plx + PLX_DOORBELL_TO_CARD);
483 writel(cmd, card->plx + PLX_MAILBOX_1);
485 if (readl(card->plx + PLX_MAILBOX_1) == 0)
498 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
500 writel(0x80, card->plx + PLX_MAILBOX_0);
501 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
502 readl(card->plx + PLX_CONTROL); /* wait for posted write */
504 writel(old_value, card->plx + PLX_CONTROL);
505 readl(card->plx + PLX_CONTROL); /* wait for posted write */
534 if (card->plx)
535 iounmap(card->plx);
639 card->plx = ioremap(plx_phy, 0x70);
640 if (!card->plx) {
651 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
675 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
725 writel(0, card->plx + PLX_MAILBOX_5);
735 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)