Lines Matching refs:slic_write
37 static void slic_write(struct spi_device *spi, u16 addr,
82 slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
85 slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
88 slic_write(spi, DS26522_RMMR_ADDR,
92 slic_write(spi, DS26522_TMMR_ADDR,
96 slic_write(spi, DS26522_RCR1_ADDR,
100 slic_write(spi, DS26522_RIOCR_ADDR,
104 slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
107 slic_write(spi, DS26522_TIOCR_ADDR,
111 slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
114 slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
117 slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
121 slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
125 slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
128 slic_write(spi, DS26522_LTITSR_ADDR,
132 slic_write(spi, DS26522_LRISMR_ADDR,
136 slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
144 slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
147 slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
148 slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
151 slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
154 slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
157 slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
161 slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
162 slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
165 slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
168 slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
175 slic_write(spi, addr, 0);
179 slic_write(spi, addr, 0);
183 slic_write(spi, addr, 0);
187 slic_write(spi, addr, 0);
192 slic_write(spi, DS26522_GTCR1_ADDR, 0x00);