Lines Matching defs:clk
93 /* Frame sync pin: input (default) or output generated off a given clk edge */
107 /* Data rate is full (default) or half the configured clk speed */
1253 int clk;
1280 clk = new_line.clock_type;
1282 clk = port->plat->set_clock(port->id, clk);
1284 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1290 port->clock_type = clk; /* Update settings */
1291 if (clk == CLOCK_INT)