Lines Matching refs:x80
46 #define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */
51 #define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */
58 #define MSCI1_OFFSET 0x80
143 #define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */
147 #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */
151 #define BARL 0x80 /* Buffer Addr Register L (chained-block) */
209 #define DST_EOM 0x80 /* End of Message */
213 #define ST_TX_EOM 0x80 /* End of frame */
218 #define ST_RX_EOM 0x80 /* End of frame */
281 #define MD0_BIT_SYNC 0x80
284 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
294 #define MD1_SADDR2 0x80
298 #define MD2_MANCHESTER 0x80
316 #define MD2_FM 0x80
324 #define CTL_URCT 0x80
340 #define RXS_DRTXC 0x80
349 #define TXS_DTRXC 0x80
359 #define CLK_PIN_OUT 0x80
394 #define ST0_TXINT 0x80
403 #define ST1_UDRN 0x80
410 #define ST2_EOM 0x80
418 #define ST3_GPI 0x80
426 #define ST4_CGPI 0x80
433 #define FST_EOMF 0x80
439 #define IE0_TXINT 0x80
450 #define IE1_UDRN 0x80
457 #define IE2_EOM 0x80
465 #define IE4_CGPI 0x80
472 #define FIE_EOMF 0x80
482 #define DSR_EOT 0x80
490 #define DIR_EOT 0x80
498 #define DIR_EOTE 0x80
505 #define DMER_DME 0x80 /* DMA Master Enable */
513 #define PCR_COTE 0x80
520 #define PCR_BURST 0x80