Lines Matching refs:sca_out
177 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
180 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
184 sca_out(0, dmac + CPB, card); /* pointer base */
194 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
201 sca_out(0x14, DMR_RX(phy_node(port)), card);
202 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
205 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
208 sca_out(0x14, DMR_TX(phy_node(port)), card);
210 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
226 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
295 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
334 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
351 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
441 sca_out(port->tmc, msci + TMC, card);
444 sca_out(port->rxs, msci + RXS, card);
445 sca_out(port->txs, msci + TXS, card);
452 sca_out(md2, msci + MD2, card);
483 sca_out(CMD_RESET, msci + CMD, card);
484 sca_out(md0, msci + MD0, card);
485 sca_out(0x00, msci + MD1, card); /* no address field check */
486 sca_out(md2, msci + MD2, card);
487 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
488 sca_out(CTL_IDLE, msci + CTL, card);
492 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
493 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
494 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
503 sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
504 sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
505 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
508 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
511 sca_out(port->tmc, msci + TMC, card); /* Restore registers */
512 sca_out(port->rxs, msci + RXS, card);
513 sca_out(port->txs, msci + TXS, card);
514 sca_out(CMD_TX_ENABLE, msci + CMD, card);
515 sca_out(CMD_RX_ENABLE, msci + CMD, card);
527 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
529 sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
532 sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
661 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
705 sca_out(wait_states, WCRL, card); /* Wait Control */
706 sca_out(wait_states, WCRM, card);
707 sca_out(wait_states, WCRH, card);
709 sca_out(0, DMER, card); /* DMA Master disable */
710 sca_out(0x03, PCR, card); /* DMA priority */
711 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
712 sca_out(0, DSR_TX(0), card);
713 sca_out(0, DSR_RX(1), card);
714 sca_out(0, DSR_TX(1), card);
715 sca_out(DMER_DME, DMER, card); /* DMA Master enable */