Lines Matching refs:ret
80 int ret;
90 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
93 if (unlikely(ret < 4)) {
94 ret = ret < 0 ? ret : -ENODATA;
97 index, ret);
98 return ret;
104 return ret;
111 int ret;
124 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
127 if (unlikely(ret < 0))
129 index, ret);
131 return ret;
165 int ret;
168 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
169 if (ret < 0) {
171 return ret;
186 int ret;
191 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
192 if (ret < 0) {
203 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
204 if (ret < 0) {
209 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
210 if (ret < 0) {
215 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
216 if (ret < 0) {
221 ret = (u16)(val & 0xFFFF);
225 return ret;
233 int ret;
238 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
239 if (ret < 0) {
245 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
246 if (ret < 0) {
257 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
258 if (ret < 0) {
263 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
264 if (ret < 0) {
300 int ret;
303 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
304 if (ret < 0) {
306 return ret;
326 int ret;
329 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
330 if (ret < 0) {
332 return ret;
349 int i, ret;
354 ret = smsc75xx_eeprom_confirm_not_busy(dev);
355 if (ret)
356 return ret;
360 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
361 if (ret < 0) {
363 return ret;
366 ret = smsc75xx_wait_eeprom(dev);
367 if (ret < 0)
368 return ret;
370 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
371 if (ret < 0) {
373 return ret;
387 int i, ret;
392 ret = smsc75xx_eeprom_confirm_not_busy(dev);
393 if (ret)
394 return ret;
398 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
399 if (ret < 0) {
401 return ret;
404 ret = smsc75xx_wait_eeprom(dev);
405 if (ret < 0)
406 return ret;
412 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
413 if (ret < 0) {
415 return ret;
420 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
421 if (ret < 0) {
423 return ret;
426 ret = smsc75xx_wait_eeprom(dev);
427 if (ret < 0)
428 return ret;
438 int i, ret;
442 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
443 if (ret < 0) {
445 return ret;
464 int i, ret;
468 ret = smsc75xx_dataport_wait_not_busy(dev);
469 if (ret < 0) {
474 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
475 if (ret < 0) {
482 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
483 if (ret < 0) {
489 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
490 if (ret < 0) {
495 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
496 if (ret < 0) {
501 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
502 if (ret < 0) {
507 ret = smsc75xx_dataport_wait_not_busy(dev);
508 if (ret < 0) {
516 return ret;
530 int ret;
538 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
539 if (ret < 0)
592 int ret;
613 ret = smsc75xx_write_reg(dev, FLOW, flow);
614 if (ret < 0) {
616 return ret;
619 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
620 if (ret < 0) {
622 return ret;
633 int ret;
639 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
640 if (ret < 0) {
642 return ret;
721 int ret;
728 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
729 if (ret < 0)
730 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
732 return ret;
794 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
795 if (ret < 0) {
796 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
797 return ret;
800 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
801 if (ret < 0) {
802 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
803 return ret;
807 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
808 if (ret < 0) {
809 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
810 return ret;
813 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
814 if (ret < 0)
815 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
817 return ret;
822 int bmcr, ret, timeout = 0;
861 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
862 if (ret < 0) {
864 return ret;
879 int ret = 0;
883 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
884 if (ret < 0) {
885 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
886 return ret;
893 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
894 if (ret < 0) {
895 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
896 return ret;
904 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
905 if (ret < 0) {
906 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
907 return ret;
912 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
913 if (ret < 0) {
914 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
915 return ret;
925 int ret;
927 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
928 if (ret < 0) {
930 return ret;
943 int ret;
955 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
956 if (ret < 0) {
958 return ret;
969 int ret;
971 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
973 if (ret < 0) {
974 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
975 return ret;
992 int ret = 0, timeout = 0;
1011 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1012 if (ret < 0) {
1013 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1014 return ret;
1019 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1020 if (ret < 0) {
1021 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1022 return ret;
1028 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1029 if (ret < 0) {
1031 ret);
1032 return ret;
1049 int ret = 0, timeout;
1053 ret = smsc75xx_wait_ready(dev, 0);
1054 if (ret < 0) {
1056 return ret;
1059 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1060 if (ret < 0) {
1061 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1062 return ret;
1067 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1068 if (ret < 0) {
1069 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1070 return ret;
1076 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1077 if (ret < 0) {
1078 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1079 return ret;
1091 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1092 if (ret < 0) {
1093 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1094 return ret;
1099 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1100 if (ret < 0) {
1101 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1102 return ret;
1108 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1109 if (ret < 0) {
1110 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1111 return ret;
1123 ret = smsc75xx_set_mac_address(dev);
1124 if (ret < 0) {
1126 return ret;
1132 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1133 if (ret < 0) {
1134 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1135 return ret;
1143 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1144 if (ret < 0) {
1145 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1146 return ret;
1149 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1150 if (ret < 0) {
1151 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1152 return ret;
1172 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
1173 if (ret < 0) {
1174 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1175 return ret;
1178 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
1179 if (ret < 0) {
1180 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1181 return ret;
1187 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
1188 if (ret < 0) {
1189 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1190 return ret;
1193 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
1194 if (ret < 0) {
1195 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1196 return ret;
1203 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1204 if (ret < 0) {
1205 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1206 return ret;
1213 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1214 if (ret < 0) {
1215 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1216 return ret;
1219 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1220 if (ret < 0) {
1221 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1222 return ret;
1230 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
1231 if (ret < 0) {
1232 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1233 return ret;
1239 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
1240 if (ret < 0) {
1241 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1242 return ret;
1247 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1248 if (ret < 0) {
1249 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1250 return ret;
1253 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
1254 if (ret < 0) {
1255 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1256 return ret;
1261 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
1262 if (ret < 0) {
1263 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1264 return ret;
1269 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
1270 if (ret < 0) {
1271 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1272 return ret;
1278 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
1279 if (ret < 0) {
1280 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1281 return ret;
1285 ret = smsc75xx_write_reg(dev, FLOW, 0);
1286 if (ret < 0) {
1287 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1288 return ret;
1291 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
1292 if (ret < 0) {
1293 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1294 return ret;
1298 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1299 if (ret < 0) {
1300 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1301 return ret;
1306 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1307 if (ret < 0) {
1308 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1309 return ret;
1312 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1313 if (ret < 0) {
1314 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1315 return ret;
1326 ret = smsc75xx_phy_initialize(dev);
1327 if (ret < 0) {
1328 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1329 return ret;
1332 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
1333 if (ret < 0) {
1334 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1335 return ret;
1341 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
1342 if (ret < 0) {
1343 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1344 return ret;
1348 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
1349 if (ret < 0) {
1350 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1351 return ret;
1355 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
1356 if (ret < 0) {
1357 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1358 return ret;
1361 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
1362 if (ret < 0) {
1363 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1364 return ret;
1369 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
1370 if (ret < 0) {
1371 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1372 return ret;
1377 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
1378 if (ret < 0) {
1379 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1380 return ret;
1385 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
1386 if (ret < 0) {
1387 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1388 return ret;
1393 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
1394 if (ret < 0) {
1396 return ret;
1399 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1400 if (ret < 0) {
1401 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1402 return ret;
1407 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1408 if (ret < 0) {
1409 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1410 return ret;
1415 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
1416 if (ret < 0) {
1417 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1418 return ret;
1423 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
1424 if (ret < 0) {
1425 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1426 return ret;
1452 int ret;
1456 ret = usbnet_get_endpoints(dev, intf);
1457 if (ret < 0) {
1458 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1459 return ret;
1485 ret = smsc75xx_wait_ready(dev, 0);
1486 if (ret < 0) {
1494 ret = smsc75xx_reset(dev);
1495 if (ret < 0) {
1496 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1513 return ret;
1537 int ret;
1539 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
1540 if (ret < 0) {
1542 return ret;
1545 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
1546 if (ret < 0) {
1548 return ret;
1551 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
1552 if (ret < 0) {
1554 return ret;
1557 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
1558 if (ret < 0) {
1560 return ret;
1563 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
1564 if (ret < 0) {
1566 return ret;
1576 int ret;
1578 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1579 if (ret < 0) {
1581 return ret;
1587 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1588 if (ret < 0) {
1590 return ret;
1602 int ret;
1604 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1605 if (ret < 0) {
1607 return ret;
1613 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1614 if (ret < 0) {
1616 return ret;
1623 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1624 if (ret < 0) {
1626 return ret;
1638 int ret;
1640 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1641 if (ret < 0) {
1643 return ret;
1649 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1650 if (ret < 0) {
1652 return ret;
1664 int ret;
1666 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
1667 if (ret < 0) {
1669 return ret;
1677 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1678 if (ret < 0) {
1680 return ret;
1686 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1687 if (ret < 0) {
1689 return ret;
1696 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1697 if (ret < 0) {
1699 return ret;
1710 int ret;
1715 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
1716 if (ret < 0) {
1718 return ret;
1722 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
1723 if (ret < 0) {
1725 return ret;
1728 ret |= mask;
1730 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1738 int ret;
1741 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1742 if (ret < 0) {
1744 return ret;
1747 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1748 if (ret < 0) {
1750 return ret;
1753 return !!(ret & BMSR_LSTATUS);
1758 int ret;
1771 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1773 if (ret < 0) {
1775 return ret;
1783 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1785 if (ret < 0) {
1787 return ret;
1799 int ret;
1801 ret = usbnet_suspend(intf, message);
1802 if (ret < 0) {
1804 return ret;
1816 ret = smsc75xx_autosuspend(dev, link_up);
1829 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1830 if (ret < 0) {
1837 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1838 if (ret < 0) {
1843 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1844 if (ret < 0) {
1851 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1852 if (ret < 0) {
1857 ret = smsc75xx_enter_suspend2(dev);
1862 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1864 if (ret < 0) {
1877 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1879 if (ret < 0) {
1884 ret |= MODE_CTRL_STS_EDPWRDOWN;
1887 PHY_MODE_CTRL_STS, ret);
1890 ret = smsc75xx_enter_suspend1(dev);
1900 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
1901 if (ret < 0) {
1913 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
1914 if (ret < 0) {
1926 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
1927 if (ret < 0) {
1934 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1935 if (ret < 0) {
1942 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1943 if (ret < 0) {
1949 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1950 if (ret < 0) {
1957 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1958 if (ret < 0) {
1964 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1965 if (ret < 0) {
1972 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1973 if (ret < 0) {
1980 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1981 if (ret < 0) {
1988 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1989 if (ret < 0) {
1997 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1998 if (ret < 0) {
2007 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2008 if (ret < 0) {
2016 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2017 if (ret < 0) {
2025 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2026 if (ret < 0) {
2034 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2035 if (ret < 0) {
2042 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2043 if (ret < 0) {
2051 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2052 if (ret < 0) {
2059 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2060 if (ret < 0) {
2067 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
2068 if (ret < 0) {
2069 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2075 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
2076 if (ret < 0) {
2077 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2083 ret = smsc75xx_enter_suspend0(dev);
2090 if (ret && PMSG_IS_AUTO(message))
2092 return ret;
2100 int ret;
2110 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2111 if (ret < 0) {
2113 return ret;
2119 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2120 if (ret < 0) {
2122 return ret;
2126 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
2127 if (ret < 0) {
2129 return ret;
2135 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2136 if (ret < 0) {
2138 return ret;
2145 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
2146 if (ret < 0) {
2148 return ret;
2153 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2154 if (ret < 0) {
2156 return ret;
2160 ret = smsc75xx_wait_ready(dev, 1);
2161 if (ret < 0) {
2163 return ret;