Lines Matching defs:data
900 * <struct fw_mac> + <info> + <firmware data>.
901 * @fw_offset: offset of the firmware binary data. The start address of
902 * the data would be the address of struct fw_mac + @fw_offset.
917 * binary data of firmware.
952 * <struct fw_phy_nc> + <info> + <firmware data>.
953 * @fw_offset: offset of the firmware binary data. The start address of
954 * the data would be the address of struct fw_phy_nc + @fw_offset.
968 * binary data of firmware.
1034 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1047 memset(data, 0xff, size);
1049 memcpy(data, tmp, size);
1057 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1062 tmp = kmemdup(data, size, GFP_KERNEL);
1084 void *data, u16 type)
1093 if ((size & 3) || !size || (index & 3) || !data)
1101 ret = get_registers(tp, index, type, limit, data);
1106 data += limit;
1109 ret = get_registers(tp, index, type, size, data);
1114 data += size;
1127 u16 size, void *data, u16 type)
1137 if ((size & 3) || !size || (index & 3) || !data)
1147 ret = set_registers(tp, index, type | byen, 4, data);
1152 data += 4;
1162 limit, data);
1167 data += limit;
1172 size, data);
1177 data += size;
1184 ret = set_registers(tp, index, type | byen, 4, data);
1197 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1199 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1203 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1205 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1209 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1211 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1216 __le32 data;
1218 generic_ocp_read(tp, index, sizeof(data), &data, type);
1220 return __le32_to_cpu(data);
1223 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1225 __le32 tmp = __cpu_to_le32(data);
1232 u32 data;
1242 data = __le32_to_cpu(tmp);
1243 data >>= (shift * 8);
1244 data &= 0xffff;
1246 return (u16)data;
1249 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1256 data &= mask;
1261 data <<= (shift * 8);
1265 tmp = __cpu_to_le32(data);
1272 u32 data;
1280 data = __le32_to_cpu(tmp);
1281 data >>= (shift * 8);
1282 data &= 0xff;
1284 return (u8)data;
1287 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1294 data &= mask;
1299 data <<= (shift * 8);
1303 tmp = __cpu_to_le32(data);
1322 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1333 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1346 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1349 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1727 static inline void *rx_agg_align(void *data)
1729 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1732 static inline void *tx_agg_align(void *data)
1734 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2315 memcpy(skb->data, rx_data, rx_frag_head_sz);
2415 static void bottom_half(unsigned long data)
2419 tp = (struct r8152 *)data;
3152 u16 data;
3164 data = sram_read(tp, SRAM_GREEN_CFG);
3165 data |= GREEN_ETH_EN;
3166 sram_write(tp, SRAM_GREEN_CFG, data);
3173 u16 data;
3177 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3178 data &= PHY_STAT_MASK;
3180 if (data == desired)
3182 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3183 data == PHY_STAT_EXT_INIT) {
3192 return data;
3209 u16 data;
3222 data = r8153_phy_status(tp, 0);
3224 switch (data) {
3230 data = r8152_mdio_read(tp, MII_BMCR);
3231 data &= ~BMCR_PDOWN;
3232 data |= BMCR_RESET;
3233 r8152_mdio_write(tp, MII_BMCR, data);
3235 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3239 if (data != PHY_STAT_LAN_ON)
3472 u16 data;
3475 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3477 data |= PATCH_REQUEST;
3479 data &= ~PATCH_REQUEST;
3480 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3512 u16 data;
3516 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3517 data &= ~PATCH_LOCK;
3518 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3779 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3799 struct fw_block *block = (struct fw_block *)&fw->data[i];
3915 __le16 *data;
3925 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3929 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3950 u8 *data;
3978 data = (u8 *)mac;
3979 data += __le16_to_cpu(mac->fw_offset);
3981 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4020 fw_hdr = (struct fw_header *)fw->data;
4026 struct fw_block *block = (struct fw_block *)&fw->data[i];
4125 u16 data;
4128 data = ocp_reg_read(tp, OCP_EEE_DATA);
4131 return data;
4134 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4137 ocp_reg_write(tp, OCP_EEE_DATA, data);
4498 u16 data;
4500 data = ocp_reg_read(tp, OCP_POWER_CFG);
4502 data |= EN_ALDPS;
4503 ocp_reg_write(tp, OCP_POWER_CFG, data);
4507 data &= ~EN_ALDPS;
4508 ocp_reg_write(tp, OCP_POWER_CFG, data);
4522 u16 data;
4533 data = ocp_reg_read(tp, OCP_EEE_CFG);
4534 data &= ~CTAP_SHORT_EN;
4535 ocp_reg_write(tp, OCP_EEE_CFG, data);
4538 data = ocp_reg_read(tp, OCP_POWER_CFG);
4539 data |= EEE_CLKDIV_EN;
4540 ocp_reg_write(tp, OCP_POWER_CFG, data);
4542 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4543 data |= EN_10M_BGOFF;
4544 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4545 data = ocp_reg_read(tp, OCP_POWER_CFG);
4546 data |= EN_10M_PLLOFF;
4547 ocp_reg_write(tp, OCP_POWER_CFG, data);
4587 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4596 u16 data;
4608 data = sram_read(tp, SRAM_GREEN_CFG);
4609 data |= R_TUNE_EN;
4610 sram_write(tp, SRAM_GREEN_CFG, data);
4611 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4612 data |= PGA_RETURN_EN;
4613 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4616 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4617 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4621 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4622 if (data != 0xffff)
4623 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4646 data = ocp_reg_read(tp, OCP_POWER_CFG);
4647 data |= EEE_CLKDIV_EN;
4648 ocp_reg_write(tp, OCP_POWER_CFG, data);
4651 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4652 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4653 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5185 void *data)
5312 u16 data;
5317 data = r8152_mdio_read(tp, MII_BMCR);
5318 if (data & BMCR_PDOWN) {
5319 data &= ~BMCR_PDOWN;
5320 r8152_mdio_write(tp, MII_BMCR, data);
5355 u16 data;
5373 data = r8153_phy_status(tp, 0);
5379 data = r8152_mdio_read(tp, MII_BMCR);
5380 if (data & BMCR_PDOWN) {
5381 data &= ~BMCR_PDOWN;
5382 r8152_mdio_write(tp, MII_BMCR, data);
5385 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5500 u16 data;
5518 data = r8153_phy_status(tp, 0);
5520 data = r8152_mdio_read(tp, MII_BMCR);
5521 if (data & BMCR_PDOWN) {
5522 data &= ~BMCR_PDOWN;
5523 r8152_mdio_write(tp, MII_BMCR, data);
5526 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6032 struct ethtool_stats *stats, u64 *data)
6044 data[0] = le64_to_cpu(tally.tx_packets);
6045 data[1] = le64_to_cpu(tally.rx_packets);
6046 data[2] = le64_to_cpu(tally.tx_errors);
6047 data[3] = le32_to_cpu(tally.rx_errors);
6048 data[4] = le16_to_cpu(tally.rx_missed);
6049 data[5] = le16_to_cpu(tally.align_errors);
6050 data[6] = le32_to_cpu(tally.tx_one_collision);
6051 data[7] = le32_to_cpu(tally.tx_multi_collision);
6052 data[8] = le64_to_cpu(tally.rx_unicast);
6053 data[9] = le64_to_cpu(tally.rx_broadcast);
6054 data[10] = le32_to_cpu(tally.rx_multicast);
6055 data[11] = le16_to_cpu(tally.tx_aborted);
6056 data[12] = le16_to_cpu(tally.tx_underrun);
6059 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6063 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
6369 struct mii_ioctl_data *data = if_mii(rq);
6381 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6386 data->val_out = r8152_mdio_read(tp, data->reg_num);
6396 r8152_mdio_write(tp, data->reg_num, data->val_in);