Lines Matching refs:phy_id
73 u32 phy_id;
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
89 phy_id = (phy_reg & 0xffff) << 16;
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
95 phy_id |= (phy_reg & 0xffff);
97 return phy_id;
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
210 /* give phy_id a chance to process reset */
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
223 dev->mii.phy_id);
265 dev->mii.phy_id = asix_get_phy_addr(dev);
273 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
359 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
394 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
454 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
486 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
507 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
509 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
511 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
520 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
524 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
528 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
605 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
609 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
629 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
636 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
720 dev->mii.phy_id = asix_get_phy_addr(dev);
796 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
799 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
803 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
809 asix_mdio_write(dev->net, dev->mii.phy_id,
812 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
827 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
830 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
831 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
834 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
835 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
836 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
844 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
863 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
932 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
934 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1084 dev->mii.phy_id = asix_get_phy_addr(dev);