Lines Matching refs:mii
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 return mii_link_ok(&dev->mii);
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
176 mii_check_media(&dev->mii, 1, 1);
177 mii_ethtool_gset(&dev->mii, &ecmd);
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
223 dev->mii.phy_id);
260 dev->mii.dev = dev->net;
261 dev->mii.mdio_read = asix_mdio_read;
262 dev->mii.mdio_write = asix_mdio_write;
263 dev->mii.phy_id_mask = 0x3f;
264 dev->mii.reg_num_mask = 0x1f;
265 dev->mii.phy_id = asix_get_phy_addr(dev);
273 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
275 mii_nway_restart(&dev->mii);
303 mii_check_media(&dev->mii, 1, 1);
304 mii_ethtool_gset(&dev->mii, &ecmd);
359 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
394 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
454 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
486 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
507 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
509 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
511 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
520 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
524 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
528 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
605 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
609 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
629 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
636 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
715 dev->mii.dev = dev->net;
716 dev->mii.mdio_read = asix_mdio_read;
717 dev->mii.mdio_write = asix_mdio_write;
718 dev->mii.phy_id_mask = 0x1f;
719 dev->mii.reg_num_mask = 0x1f;
720 dev->mii.phy_id = asix_get_phy_addr(dev);
796 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
799 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
803 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
809 asix_mdio_write(dev->net, dev->mii.phy_id,
812 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
827 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
830 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
831 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
834 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
835 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
836 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
844 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
863 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
932 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
934 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
938 mii_nway_restart(&dev->mii);
963 mii_check_media(&dev->mii, 1, 1);
964 mii_ethtool_gset(&dev->mii, &ecmd);
1078 dev->mii.dev = dev->net;
1079 dev->mii.mdio_read = asix_mdio_read;
1080 dev->mii.mdio_write = asix_mdio_write;
1081 dev->mii.phy_id_mask = 0x1f;
1082 dev->mii.reg_num_mask = 0xff;
1083 dev->mii.supports_gmii = 1;
1084 dev->mii.phy_id = asix_get_phy_addr(dev);