Lines Matching defs:phydev
13 * @phydev: target phy_device struct
15 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
20 if (phydev->duplex != DUPLEX_FULL)
23 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
27 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
38 switch (phydev->speed) {
70 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
74 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
78 return genphy_c45_an_disable_aneg(phydev);
84 * @phydev: target phy_device struct
86 * Configure advertisement registers based on modes set in phydev->advertising
91 int genphy_c45_an_config_aneg(struct phy_device *phydev)
96 linkmode_and(phydev->advertising, phydev->advertising,
97 phydev->supported);
99 changed = genphy_config_eee_advert(phydev);
101 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
103 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
112 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
114 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
129 * @phydev: target phy_device struct
136 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
139 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
146 * @phydev: target phy_device struct
152 int genphy_c45_restart_aneg(struct phy_device *phydev)
154 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
161 * @phydev: target phy_device struct
168 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
174 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
183 return genphy_c45_restart_aneg(phydev);
191 * @phydev: target phy_device struct
200 int genphy_c45_aneg_done(struct phy_device *phydev)
202 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
210 * @phydev: target phy_device struct
213 * that the link is up, set phydev->link to 1. If an error is encountered,
216 int genphy_c45_read_link(struct phy_device *phydev)
222 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
223 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
231 phydev->link = 0;
245 if (!phy_polling_mode(phydev) || !phydev->link) {
246 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
253 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
261 phydev->link = link;
269 * @phydev: target phy_device struct
273 * in @phydev. This assumes that the auto-negotiation MMD is present, and
277 int genphy_c45_read_lpa(struct phy_device *phydev)
281 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
287 phydev->lp_advertising);
288 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
289 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
290 phydev->pause = 0;
291 phydev->asym_pause = 0;
296 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
300 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
304 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
305 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
306 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
309 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
313 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
321 * @phydev: target phy_device struct
323 int genphy_c45_read_pma(struct phy_device *phydev)
327 linkmode_zero(phydev->lp_advertising);
329 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
335 phydev->speed = SPEED_10;
338 phydev->speed = SPEED_100;
341 phydev->speed = SPEED_1000;
344 phydev->speed = SPEED_2500;
347 phydev->speed = SPEED_5000;
350 phydev->speed = SPEED_10000;
353 phydev->speed = SPEED_UNKNOWN;
357 phydev->duplex = DUPLEX_FULL;
365 * @phydev: target phy_device struct
367 int genphy_c45_read_mdix(struct phy_device *phydev)
371 if (phydev->speed == SPEED_10000) {
372 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
379 phydev->mdix = ETH_TP_MDI;
383 phydev->mdix = ETH_TP_MDI_X;
387 phydev->mdix = ETH_TP_MDI_INVALID;
398 * @phydev: target phy_device struct
407 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
411 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
412 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
413 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
419 phydev->supported);
422 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
427 phydev->supported,
431 phydev->supported,
435 phydev->supported,
439 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
444 phydev->supported,
447 phydev->supported,
450 phydev->supported,
453 phydev->supported,
456 phydev->supported,
459 phydev->supported,
463 phydev->supported,
466 phydev->supported,
470 phydev->supported,
473 phydev->supported,
477 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
483 phydev->supported,
487 phydev->supported,
498 * @phydev: target phy_device struct
502 int genphy_c45_read_status(struct phy_device *phydev)
506 ret = genphy_c45_read_link(phydev);
510 phydev->speed = SPEED_UNKNOWN;
511 phydev->duplex = DUPLEX_UNKNOWN;
512 phydev->pause = 0;
513 phydev->asym_pause = 0;
515 if (phydev->autoneg == AUTONEG_ENABLE) {
516 ret = genphy_c45_read_lpa(phydev);
520 phy_resolve_aneg_linkmode(phydev);
522 ret = genphy_c45_read_pma(phydev);
531 * @phydev: target phy_device struct
537 int genphy_c45_config_aneg(struct phy_device *phydev)
542 if (phydev->autoneg == AUTONEG_DISABLE)
543 return genphy_c45_pma_setup_forced(phydev);
545 ret = genphy_c45_an_config_aneg(phydev);
551 return genphy_c45_check_and_restart_aneg(phydev, changed);
557 int gen10g_config_aneg(struct phy_device *phydev)