Lines Matching refs:EGRESS
58 EGRESS,
74 case EGRESS:
124 case EGRESS:
195 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i),
199 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3),
348 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT);
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
353 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG);
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val);
971 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */
980 vsc85xx_eth1_next_comp(phydev, EGRESS,
986 vsc85xx_eth1_next_comp(phydev, EGRESS,
992 vsc85xx_ip1_next_comp(phydev, EGRESS,
1003 vsc85xx_eth1_conf(phydev, EGRESS,
1005 vsc85xx_ip1_conf(phydev, EGRESS,
1007 vsc85xx_ptp_conf(phydev, EGRESS, one_step,
1455 vsc85xx_ts_disable_flows(phydev, EGRESS);
1460 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */
1481 vsc85xx_eth_cmp1_init(phydev, EGRESS);
1482 vsc85xx_ip_cmp1_init(phydev, EGRESS);
1483 vsc85xx_ptp_cmp_init(phydev, EGRESS);