Lines Matching refs:val
25 u32 val, val_l = 0, val_h = 0;
49 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
50 } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
62 enum macsec_bank bank, u32 reg, u32 val)
80 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
81 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
89 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
90 } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
156 u32 val;
162 val = vsc8584_macsec_phy_read(phydev, bank,
164 val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
167 val);
178 u32 val;
196 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
197 val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
198 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
206 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
207 val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
208 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
221 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
222 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
223 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
247 u32 val;
254 val = vsc8584_macsec_phy_read(phydev, bank,
256 val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
257 val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
260 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
262 val = vsc8584_macsec_phy_read(phydev, bank,
264 val |= 0xffff;
266 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
268 val = vsc8584_macsec_phy_read(phydev, bank,
271 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
274 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
279 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
292 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
293 val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
294 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
296 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
297 val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
298 val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
299 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
307 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
308 val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
309 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
323 u32 val;
335 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
336 val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
339 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
345 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
347 val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
349 val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
352 MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
354 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
355 val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
356 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
360 val = vsc8584_macsec_phy_read(phydev, proc_bank,
362 val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
363 val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
365 MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
375 u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
421 val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
430 val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
432 val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
434 val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
437 val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
439 val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
441 val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
445 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
465 u32 val, idx = flow->index;
475 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
476 val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
477 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
484 u32 val, idx = flow->index;
490 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
491 val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
492 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
1019 u32 val;
1024 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1026 if (val == 0xffffffff) {