Lines Matching defs:phydev
114 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
116 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
119 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
121 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
124 static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev)
126 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310)
127 return mv3310_hwmon_read_temp_reg(phydev);
129 return mv2110_hwmon_read_temp_reg(phydev);
135 struct phy_device *phydev = dev_get_drvdata(dev);
144 temp = mv10g_hwmon_read_temp_reg(phydev);
192 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
197 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
200 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
207 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
211 static int mv3310_hwmon_probe(struct phy_device *phydev)
213 struct device *dev = &phydev->mdio.dev;
214 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
230 ret = mv3310_hwmon_config(phydev, true);
235 priv->hwmon_name, phydev,
241 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
246 static int mv3310_hwmon_probe(struct phy_device *phydev)
252 static int mv3310_power_down(struct phy_device *phydev)
254 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
258 static int mv3310_power_up(struct phy_device *phydev)
260 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
263 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
273 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
277 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
281 static int mv3310_reset(struct phy_device *phydev, u32 unit)
285 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
290 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
296 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
300 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
318 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
341 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
344 err = mv3310_reset(phydev, MV_PCS_BASE_T);
351 struct phy_device *phydev = upstream;
355 sfp_parse_support(phydev->sfp_bus, id, support);
356 iface = sfp_select_interface(phydev->sfp_bus, support);
359 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
371 static int mv3310_probe(struct phy_device *phydev)
377 if (!phydev->is_c45 ||
378 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
381 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
386 dev_warn(&phydev->mdio.dev,
391 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
395 dev_set_drvdata(&phydev->mdio.dev, priv);
397 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
403 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
409 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
414 ret = mv3310_power_down(phydev);
418 ret = mv3310_hwmon_probe(phydev);
422 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
425 static void mv3310_remove(struct phy_device *phydev)
427 mv3310_hwmon_config(phydev, false);
430 static int mv3310_suspend(struct phy_device *phydev)
432 return mv3310_power_down(phydev);
435 static int mv3310_resume(struct phy_device *phydev)
439 ret = mv3310_power_up(phydev);
443 return mv3310_hwmon_config(phydev, true);
453 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
455 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
459 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
463 static int mv3310_config_init(struct phy_device *phydev)
465 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
470 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
471 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
472 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
473 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
474 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
477 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
480 err = mv3310_power_up(phydev);
484 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
491 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
494 static int mv3310_get_features(struct phy_device *phydev)
498 ret = genphy_c45_pma_read_abilities(phydev);
502 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
503 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
509 phydev->supported,
513 phydev->supported,
520 static int mv3310_config_mdix(struct phy_device *phydev)
525 switch (phydev->mdix_ctrl) {
539 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
542 err = mv3310_reset(phydev, MV_PCS_BASE_T);
547 static int mv3310_config_aneg(struct phy_device *phydev)
553 ret = mv3310_config_mdix(phydev);
557 if (phydev->autoneg == AUTONEG_DISABLE)
558 return genphy_c45_pma_setup_forced(phydev);
560 ret = genphy_c45_an_config_aneg(phydev);
569 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
570 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
577 return genphy_c45_check_and_restart_aneg(phydev, changed);
580 static int mv3310_aneg_done(struct phy_device *phydev)
584 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
591 return genphy_c45_aneg_done(phydev);
594 static void mv3310_update_interface(struct phy_device *phydev)
596 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
603 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
607 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
608 phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
609 phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
610 phydev->link) {
614 * setting phydev->interface to communicate this to the MAC.
617 switch (phydev->speed) {
619 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
622 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
627 phydev->interface = PHY_INTERFACE_MODE_SGMII;
636 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
638 phydev->link = 1;
639 phydev->speed = SPEED_10000;
640 phydev->duplex = DUPLEX_FULL;
641 phydev->port = PORT_FIBRE;
646 static int mv3310_read_status_copper(struct phy_device *phydev)
650 val = genphy_c45_read_link(phydev);
654 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
658 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
664 phydev->link = 0;
675 phydev->speed = SPEED_10000;
679 phydev->speed = SPEED_5000;
683 phydev->speed = SPEED_2500;
687 phydev->speed = SPEED_1000;
691 phydev->speed = SPEED_100;
695 phydev->speed = SPEED_10;
699 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
701 phydev->port = PORT_TP;
702 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
706 val = genphy_c45_read_lpa(phydev);
711 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
715 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
718 phy_resolve_aneg_pause(phydev);
724 static int mv3310_read_status(struct phy_device *phydev)
728 phydev->speed = SPEED_UNKNOWN;
729 phydev->duplex = DUPLEX_UNKNOWN;
730 linkmode_zero(phydev->lp_advertising);
731 phydev->link = 0;
732 phydev->pause = 0;
733 phydev->asym_pause = 0;
734 phydev->mdix = ETH_TP_MDI_INVALID;
736 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
741 err = mv3310_read_status_10gbaser(phydev);
743 err = mv3310_read_status_copper(phydev);
747 if (phydev->link)
748 mv3310_update_interface(phydev);
753 static int mv3310_get_tunable(struct phy_device *phydev,
758 return mv3310_get_edpd(phydev, data);
764 static int mv3310_set_tunable(struct phy_device *phydev,
769 return mv3310_set_edpd(phydev, *(u16 *)data);