Lines Matching defs:phydev
78 static int dp83811_ack_interrupt(struct phy_device *phydev)
82 err = phy_read(phydev, MII_DP83811_INT_STAT1);
86 err = phy_read(phydev, MII_DP83811_INT_STAT2);
90 err = phy_read(phydev, MII_DP83811_INT_STAT3);
97 static int dp83811_set_wol(struct phy_device *phydev,
100 struct net_device *ndev = phydev->attached_dev;
113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
120 value = phy_read_mmd(phydev, DP83811_DEVADDR,
128 phy_write_mmd(phydev, DP83811_DEVADDR,
131 phy_write_mmd(phydev, DP83811_DEVADDR,
134 phy_write_mmd(phydev, DP83811_DEVADDR,
143 phy_read(phydev, MII_DP83811_INT_STAT1);
148 return phy_write_mmd(phydev, DP83811_DEVADDR,
151 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
157 static void dp83811_get_wol(struct phy_device *phydev,
166 value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
172 sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
177 sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
182 sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
195 static int dp83811_config_intr(struct phy_device *phydev)
199 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
200 misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
213 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
217 misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
228 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
232 misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
240 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
243 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
247 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
251 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
257 static int dp83811_config_aneg(struct phy_device *phydev)
261 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
262 value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
263 if (phydev->autoneg == AUTONEG_ENABLE) {
264 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
269 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
276 return genphy_config_aneg(phydev);
279 static int dp83811_config_init(struct phy_device *phydev)
283 value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
284 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
285 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
288 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
298 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
302 static int dp83811_phy_reset(struct phy_device *phydev)
306 err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
313 static int dp83811_suspend(struct phy_device *phydev)
317 value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
320 genphy_suspend(phydev);
325 static int dp83811_resume(struct phy_device *phydev)
327 genphy_resume(phydev);
329 phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,