Lines Matching defs:phydev
155 static int dp83869_read_status(struct phy_device *phydev)
157 struct dp83869_private *dp83869 = phydev->priv;
160 ret = genphy_read_status(phydev);
164 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
165 if (phydev->link) {
167 phydev->speed = SPEED_100;
169 phydev->speed = SPEED_UNKNOWN;
170 phydev->duplex = DUPLEX_UNKNOWN;
177 static int dp83869_ack_interrupt(struct phy_device *phydev)
179 int err = phy_read(phydev, MII_DP83869_ISR);
187 static int dp83869_config_intr(struct phy_device *phydev)
191 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
192 micr_status = phy_read(phydev, MII_DP83869_MICR);
204 return phy_write(phydev, MII_DP83869_MICR, micr_status);
207 return phy_write(phydev, MII_DP83869_MICR, micr_status);
210 static int dp83869_set_wol(struct phy_device *phydev,
213 struct net_device *ndev = phydev->attached_dev;
218 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
222 val_micr = phy_read(phydev, MII_DP83869_MICR);
238 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
244 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
250 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
262 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
268 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
273 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
302 return phy_write(phydev, MII_DP83869_MICR, val_micr);
305 static void dp83869_get_wol(struct phy_device *phydev,
314 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
316 phydev_err(phydev, "Failed to read RX CFG\n");
330 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
333 phydev_err(phydev, "Failed to read RX SOP 1\n");
340 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
343 phydev_err(phydev, "Failed to read RX SOP 2\n");
350 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
353 phydev_err(phydev, "Failed to read RX SOP 3\n");
367 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
371 val = phy_read(phydev, DP83869_CFG2);
400 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
408 return phy_clear_bits(phydev, DP83869_CFG2,
425 phydev_err(phydev,
433 return phy_modify(phydev, DP83869_CFG2,
438 static int dp83869_get_tunable(struct phy_device *phydev,
443 return dp83869_get_downshift(phydev, data);
449 static int dp83869_set_tunable(struct phy_device *phydev,
454 return dp83869_set_downshift(phydev, *(const u8 *)data);
460 static int dp83869_config_port_mirroring(struct phy_device *phydev)
462 struct dp83869_private *dp83869 = phydev->priv;
465 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
469 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
474 static int dp83869_set_strapped_mode(struct phy_device *phydev)
476 struct dp83869_private *dp83869 = phydev->priv;
479 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
493 static int dp83869_of_init(struct phy_device *phydev)
495 struct dp83869_private *dp83869 = phydev->priv;
496 struct device *dev = &phydev->mdio.dev;
518 ret = dp83869_set_strapped_mode(phydev);
532 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
552 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
558 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
567 static int dp83869_of_init(struct phy_device *phydev)
569 return dp83869_set_strapped_mode(phydev);
573 static int dp83869_configure_rgmii(struct phy_device *phydev,
578 if (phy_interface_is_rgmii(phydev)) {
579 val = phy_read(phydev, MII_DP83869_PHYCTRL);
587 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
593 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
602 static int dp83869_configure_fiber(struct phy_device *phydev,
609 linkmode_and(phydev->advertising, phydev->advertising,
610 phydev->supported);
612 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
613 linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
617 phydev->supported);
620 phydev->supported);
622 phydev->supported);
625 bmcr = phy_read(phydev, MII_BMCR);
629 phydev->autoneg = AUTONEG_DISABLE;
630 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
631 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
634 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
641 linkmode_or(phydev->advertising, phydev->advertising,
642 phydev->supported);
647 static int dp83869_configure_mode(struct phy_device *phydev,
660 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
665 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
675 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
680 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
684 ret = dp83869_configure_rgmii(phydev, dp83869);
689 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
695 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
702 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
707 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
713 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
719 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
724 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
728 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
736 ret = dp83869_configure_fiber(phydev, dp83869);
745 static int dp83869_config_init(struct phy_device *phydev)
747 struct dp83869_private *dp83869 = phydev->priv;
751 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
756 ret = dp83869_configure_mode(phydev, dp83869);
761 if (phy_interrupt_is_valid(phydev)) {
762 val = phy_read(phydev, DP83869_CFG4);
764 phy_write(phydev, DP83869_CFG4, val);
768 dp83869_config_port_mirroring(phydev);
772 ret = phy_modify_mmd(phydev,
778 if (phy_interface_is_rgmii(phydev)) {
779 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
785 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
789 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
793 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
796 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
799 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
806 static int dp83869_probe(struct phy_device *phydev)
811 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
816 phydev->priv = dp83869;
818 ret = dp83869_of_init(phydev);
824 phydev->port = PORT_FIBRE;
826 return dp83869_config_init(phydev);
829 static int dp83869_phy_reset(struct phy_device *phydev)
833 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
842 return dp83869_config_init(phydev);