Lines Matching defs:phydev
172 static int dp83867_ack_interrupt(struct phy_device *phydev)
174 int err = phy_read(phydev, MII_DP83867_ISR);
182 static int dp83867_set_wol(struct phy_device *phydev,
185 struct net_device *ndev = phydev->attached_dev;
189 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
190 val_micr = phy_read(phydev, MII_DP83867_MICR);
203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
243 phy_write(phydev, MII_DP83867_MICR, val_micr);
248 static void dp83867_get_wol(struct phy_device *phydev,
257 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
279 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
291 static int dp83867_config_intr(struct phy_device *phydev)
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
296 micr_status = phy_read(phydev, MII_DP83867_MICR);
308 return phy_write(phydev, MII_DP83867_MICR, micr_status);
312 return phy_write(phydev, MII_DP83867_MICR, micr_status);
315 static int dp83867_read_status(struct phy_device *phydev)
317 int status = phy_read(phydev, MII_DP83867_PHYSTS);
320 ret = genphy_read_status(phydev);
328 phydev->duplex = DUPLEX_FULL;
330 phydev->duplex = DUPLEX_HALF;
333 phydev->speed = SPEED_1000;
335 phydev->speed = SPEED_100;
337 phydev->speed = SPEED_10;
342 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
346 val = phy_read(phydev, DP83867_CFG2);
375 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
383 return phy_clear_bits(phydev, DP83867_CFG2,
400 phydev_err(phydev,
408 return phy_modify(phydev, DP83867_CFG2,
413 static int dp83867_get_tunable(struct phy_device *phydev,
418 return dp83867_get_downshift(phydev, data);
424 static int dp83867_set_tunable(struct phy_device *phydev,
429 return dp83867_set_downshift(phydev, *(const u8 *)data);
435 static int dp83867_config_port_mirroring(struct phy_device *phydev)
438 (struct dp83867_private *)phydev->priv;
441 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
444 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
449 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
451 struct dp83867_private *dp83867 = phydev->priv;
456 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
457 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
466 phydev_warn(phydev,
473 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
474 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
476 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
481 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
482 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
484 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
492 static int dp83867_of_init(struct phy_device *phydev)
494 struct dp83867_private *dp83867 = phydev->priv;
495 struct device *dev = &phydev->mdio.dev;
513 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
536 phydev_err(phydev,
546 phydev_err(phydev,
569 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
580 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
588 static int dp83867_of_init(struct phy_device *phydev)
594 static int dp83867_probe(struct phy_device *phydev)
598 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
603 phydev->priv = dp83867;
605 return dp83867_of_init(phydev);
608 static int dp83867_config_init(struct phy_device *phydev)
610 struct dp83867_private *dp83867 = phydev->priv;
615 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
620 ret = dp83867_verify_rgmii_cfg(phydev);
626 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
629 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
635 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
643 if (phy_interface_is_rgmii(phydev) ||
644 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
645 val = phy_read(phydev, MII_DP83867_PHYCTRL);
653 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
659 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
664 if (phy_interface_is_rgmii(phydev)) {
665 val = phy_read(phydev, MII_DP83867_PHYCTRL);
679 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
683 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
694 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
697 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
700 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
703 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
706 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
715 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
721 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
725 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
732 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
743 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
751 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
760 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
767 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
771 val = phy_read(phydev, DP83867_CFG3);
773 if (phy_interrupt_is_valid(phydev))
777 phy_write(phydev, DP83867_CFG3, val);
780 dp83867_config_port_mirroring(phydev);
794 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
801 static int dp83867_phy_reset(struct phy_device *phydev)
805 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
811 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
820 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
825 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
834 static void dp83867_link_change_notify(struct phy_device *phydev)
847 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
850 val = phy_clear_bits(phydev, DP83867_CFG2,
855 phy_set_bits(phydev, DP83867_CFG2,