Lines Matching defs:phydev
100 struct phy_device *phydev;
211 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
214 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
218 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
220 struct dp83640_private *dp83640 = phydev->priv;
224 broadcast_write(phydev, PAGESEL, page);
227 val = phy_read(phydev, regnum);
233 static void ext_write(int broadcast, struct phy_device *phydev,
236 struct dp83640_private *dp83640 = phydev->priv;
239 broadcast_write(phydev, PAGESEL, page);
243 broadcast_write(phydev, regnum, val);
245 phy_write(phydev, regnum, val);
300 struct phy_device *phydev = dp83640->phydev;
324 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
325 ext_write(0, phydev, PAGE4, PTP_CTL, val);
338 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
342 ext_write(0, phydev, PAGE4, PTP_CTL, val);
343 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
344 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
345 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
346 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
347 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
348 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
351 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
352 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
358 ext_write(0, phydev, PAGE4, PTP_CTL, val);
370 struct phy_device *phydev = clock->chosen->phydev;
391 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
392 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
403 struct phy_device *phydev = clock->chosen->phydev;
413 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
425 struct phy_device *phydev = clock->chosen->phydev;
430 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
432 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
433 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
434 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
435 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
450 struct phy_device *phydev = clock->chosen->phydev;
455 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
467 struct phy_device *phydev = clock->chosen->phydev;
503 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
541 static void enable_status_frames(struct phy_device *phydev, bool on)
543 struct dp83640_private *dp83640 = phydev->priv;
554 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
555 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
559 if (!phydev->attached_dev) {
560 phydev_warn(phydev,
566 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
567 phydev_warn(phydev, "failed to add mc address\n");
569 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
570 phydev_warn(phydev, "failed to delete mc address\n");
607 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
610 phy_write(phydev, PAGESEL, 0);
611 val = phy_read(phydev, PHYCR2);
616 phy_write(phydev, PHYCR2, val);
617 phy_write(phydev, PAGESEL, init_page);
627 struct phy_device *master = clock->chosen->phydev;
644 enable_broadcast(tmp->phydev, clock->page, 1);
645 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
646 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
647 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
663 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
705 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
706 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
707 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
708 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
709 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
710 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
711 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
712 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
714 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
718 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
726 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
1034 struct phy_device *phydev)
1039 if (chosen_phy == phydev->mdio.addr)
1098 static int dp83640_soft_reset(struct phy_device *phydev)
1102 ret = genphy_soft_reset(phydev);
1115 static int dp83640_config_init(struct phy_device *phydev)
1117 struct dp83640_private *dp83640 = phydev->priv;
1124 enable_broadcast(phydev, clock->page, 1);
1128 enable_status_frames(phydev, true);
1131 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1137 static int dp83640_ack_interrupt(struct phy_device *phydev)
1139 int err = phy_read(phydev, MII_DP83640_MISR);
1147 static int dp83640_config_intr(struct phy_device *phydev)
1153 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1154 misr = phy_read(phydev, MII_DP83640_MISR);
1162 err = phy_write(phydev, MII_DP83640_MISR, misr);
1166 micr = phy_read(phydev, MII_DP83640_MICR);
1172 return phy_write(phydev, MII_DP83640_MICR, micr);
1174 micr = phy_read(phydev, MII_DP83640_MICR);
1180 err = phy_write(phydev, MII_DP83640_MICR, micr);
1184 misr = phy_read(phydev, MII_DP83640_MISR);
1192 return phy_write(phydev, MII_DP83640_MISR, misr);
1279 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1280 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1412 static int dp83640_probe(struct phy_device *phydev)
1418 if (phydev->mdio.addr == BROADCAST_ADDR)
1421 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1429 dp83640->phydev = phydev;
1441 phydev->mii_ts = &dp83640->mii_ts;
1442 phydev->priv = dp83640;
1450 if (choose_this_phy(clock, phydev)) {
1453 &phydev->mdio.dev);
1473 static void dp83640_remove(struct phy_device *phydev)
1477 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1479 if (phydev->mdio.addr == BROADCAST_ADDR)
1482 phydev->mii_ts = NULL;
1484 enable_status_frames(phydev, false);