Lines Matching defs:set
127 /* Select 1000BASE-X register set (primary SerDes) */
155 /* Select copper register set */
269 * Here, bit 0 _disables_ CLK125 when set.
270 * This bit is set by default.
276 /* Here, bit 0 _enables_ CLK125 when set */
486 * Select 1000BASE-X register set (primary SerDes)
542 /* Then we can set up the delay. */
575 /* Bit 0 of the SerDes 100-FX Control register, when set
577 * When this bit is set to 0, it sets the GMII/RGMII ->
599 /* Then we can set up the delay. */
617 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
625 return phy_write(phydev, reg, val | set);