Lines Matching defs:phydev
20 #define BRCM_PHY_MODEL(phydev) \
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
23 #define BRCM_PHY_REV(phydev) \
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
30 static int bcm54xx_config_clock_delay(struct phy_device *phydev)
35 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
37 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
38 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
43 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
47 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
53 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
54 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
55 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
59 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
60 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
64 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
71 static int bcm54210e_config_init(struct phy_device *phydev)
75 bcm54xx_config_clock_delay(phydev);
77 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
78 val = phy_read(phydev, MII_CTRL1000);
80 phy_write(phydev, MII_CTRL1000, val);
86 static int bcm54612e_config_init(struct phy_device *phydev)
90 bcm54xx_config_clock_delay(phydev);
93 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
96 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
97 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
107 static int bcm54616s_config_init(struct phy_device *phydev)
111 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
112 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
117 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
122 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
128 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
132 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
137 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
143 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
146 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
151 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
157 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
162 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
166 static int bcm50610_a0_workaround(struct phy_device *phydev)
170 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
176 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
181 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
186 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
197 static int bcm54xx_phydsp_config(struct phy_device *phydev)
202 err = bcm54xx_auxctl_write(phydev,
209 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
210 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
212 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
217 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
218 err = bcm50610_a0_workaround(phydev);
224 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
227 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
232 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
237 err2 = bcm54xx_auxctl_write(phydev,
245 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
252 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
253 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
254 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
255 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
256 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
259 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
265 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
266 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
267 BRCM_PHY_REV(phydev) >= 0x3) {
274 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
275 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
283 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
288 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
289 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
290 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
297 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
299 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
305 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
311 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
314 static int bcm54xx_config_init(struct phy_device *phydev)
318 reg = phy_read(phydev, MII_BCM54XX_ECR);
324 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
332 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
336 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
337 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
338 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
339 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
341 bcm54xx_adjust_rxrefclk(phydev);
343 switch (BRCM_PHY_MODEL(phydev)) {
346 err = bcm54xx_config_clock_delay(phydev);
349 err = bcm54210e_config_init(phydev);
352 err = bcm54612e_config_init(phydev);
355 err = bcm54616s_config_init(phydev);
359 val = bcm_phy_read_exp(phydev,
362 err = bcm_phy_write_exp(phydev,
370 bcm54xx_phydsp_config(phydev);
378 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
383 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
388 static int bcm54xx_resume(struct phy_device *phydev)
395 ret = genphy_resume(phydev);
404 return bcm54xx_config_init(phydev);
407 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
412 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
418 static int bcm54811_config_init(struct phy_device *phydev)
423 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
425 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
430 err = bcm54xx_config_init(phydev);
433 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
434 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
435 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
444 static int bcm5482_config_init(struct phy_device *phydev)
448 err = bcm54xx_config_init(phydev);
450 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
454 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
455 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
464 err = bcm_phy_read_exp(phydev, reg);
467 err = bcm_phy_write_exp(phydev, reg, err |
477 err = bcm_phy_read_exp(phydev, reg);
480 err = bcm_phy_write_exp(phydev, reg,
488 reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
489 bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
496 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
506 phydev->autoneg = AUTONEG_DISABLE;
507 phydev->speed = SPEED_1000;
508 phydev->duplex = DUPLEX_FULL;
514 static int bcm5482_read_status(struct phy_device *phydev)
518 err = genphy_read_status(phydev);
520 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
525 if (phydev->link) {
526 phydev->speed = SPEED_1000;
527 phydev->duplex = DUPLEX_FULL;
534 static int bcm5481_config_aneg(struct phy_device *phydev)
536 struct device_node *np = phydev->mdio.dev.of_node;
540 ret = genphy_config_aneg(phydev);
543 bcm54xx_config_clock_delay(phydev);
547 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
556 static int bcm54616s_probe(struct phy_device *phydev)
560 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
571 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
581 phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
583 phydev->port = PORT_FIBRE;
589 static int bcm54616s_config_aneg(struct phy_device *phydev)
594 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
595 ret = genphy_c37_config_aneg(phydev);
597 ret = genphy_config_aneg(phydev);
600 bcm54xx_config_clock_delay(phydev);
605 static int bcm54616s_read_status(struct phy_device *phydev)
609 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
610 err = genphy_c37_read_status(phydev);
612 err = genphy_read_status(phydev);
617 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
621 val = phy_read(phydev, reg);
625 return phy_write(phydev, reg, val | set);
628 static int brcm_fet_config_init(struct phy_device *phydev)
633 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
653 err = phy_read(phydev, MII_BMCR);
657 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
668 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
673 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
679 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
684 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
693 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
698 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
703 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
705 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
711 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
718 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
723 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
730 static int brcm_fet_config_intr(struct phy_device *phydev)
734 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
738 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
743 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
751 static int bcm53xx_phy_probe(struct phy_device *phydev)
755 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
759 phydev->priv = priv;
761 priv->stats = devm_kcalloc(&phydev->mdio.dev,
762 bcm_phy_get_sset_count(phydev), sizeof(u64),
770 static void bcm53xx_phy_get_stats(struct phy_device *phydev,
773 struct bcm53xx_phy_priv *priv = phydev->priv;
775 bcm_phy_get_stats(phydev, priv->stats, stats, data);