Lines Matching defs:phydev
51 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
54 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
57 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
60 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
63 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
66 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
69 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
72 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
77 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
83 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
86 bcm_phy_r_rc_cal_reset(phydev);
91 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
94 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
97 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
100 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
105 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
111 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
114 bcm_phy_r_rc_cal_reset(phydev);
119 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
122 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
125 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
128 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
131 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
134 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
137 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
139 bcm_phy_r_rc_cal_reset(phydev);
144 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
146 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
147 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
155 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
158 phydev_name(phydev), phydev->drv->name, rev, patch);
165 phy_read(phydev, MII_BMSR);
170 ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
173 ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
179 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
182 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
191 ret = bcm_phy_enable_jumbo(phydev);
195 ret = bcm_phy_downshift_get(phydev, &count);
200 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
204 return bcm_phy_enable_apd(phydev, true);
207 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
212 ret = bcm7xxx_28nm_config_init(phydev);
221 return genphy_config_aneg(phydev);
255 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
285 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
301 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
306 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
312 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
318 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
326 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
331 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
360 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
366 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
370 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
383 phy_write(phydev, MII_BMCR,
389 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
391 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
395 phydev_name(phydev), phydev->drv->name, rev);
402 phy_read(phydev, MII_BMSR);
406 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
411 ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
415 return bcm7xxx_28nm_ephy_apd_enable(phydev);
445 static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
456 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
462 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
466 ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT);
470 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
475 static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
486 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
492 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
497 __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val);
501 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
505 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
510 ret = bcm7xxx_28nm_ephy_config_init(phydev);
514 return genphy_config_aneg(phydev);
517 static int bcm7xxx_config_init(struct phy_device *phydev)
522 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
523 phy_read(phydev, MII_BCM7XXX_AUX_MODE);
526 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
532 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
536 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
538 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
541 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
551 static int bcm7xxx_suspend(struct phy_device *phydev)
568 ret = phy_write(phydev,
578 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
584 return bcm_phy_downshift_get(phydev, (u8 *)data);
590 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
599 ret = bcm_phy_downshift_set(phydev, count);
612 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
616 return genphy_restart_aneg(phydev);
619 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
622 struct bcm7xxx_phy_priv *priv = phydev->priv;
624 bcm_phy_get_stats(phydev, priv->stats, stats, data);
627 static int bcm7xxx_28nm_probe(struct phy_device *phydev)
632 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
636 phydev->priv = priv;
638 priv->stats = devm_kcalloc(&phydev->mdio.dev,
639 bcm_phy_get_sset_count(phydev), sizeof(u64),
644 priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL);
658 phy_read(phydev, MII_BMSR);
663 static void bcm7xxx_28nm_remove(struct phy_device *phydev)
665 struct bcm7xxx_phy_priv *priv = phydev->priv;