Lines Matching defs:MII_BCM7XXX_TEST
25 #define MII_BCM7XXX_TEST 0x1f
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
331 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
456 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
470 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
486 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
501 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
526 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
541 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
558 { MII_BCM7XXX_TEST, 0x008b },
561 { MII_BCM7XXX_TEST, 0x000f },
563 { MII_BCM7XXX_TEST, 0x000b },