Lines Matching defs:phydev
165 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
169 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
173 return phy_read(phydev, AT803X_DEBUG_DATA);
176 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
182 ret = at803x_debug_reg_read(phydev, reg);
190 return phy_write(phydev, AT803X_DEBUG_DATA, val);
193 static int at803x_enable_rx_delay(struct phy_device *phydev)
195 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
199 static int at803x_enable_tx_delay(struct phy_device *phydev)
201 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
205 static int at803x_disable_rx_delay(struct phy_device *phydev)
207 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
211 static int at803x_disable_tx_delay(struct phy_device *phydev)
213 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
218 static void at803x_context_save(struct phy_device *phydev,
221 context->bmcr = phy_read(phydev, MII_BMCR);
222 context->advertise = phy_read(phydev, MII_ADVERTISE);
223 context->control1000 = phy_read(phydev, MII_CTRL1000);
224 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
225 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
226 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
230 static void at803x_context_restore(struct phy_device *phydev,
233 phy_write(phydev, MII_BMCR, context->bmcr);
234 phy_write(phydev, MII_ADVERTISE, context->advertise);
235 phy_write(phydev, MII_CTRL1000, context->control1000);
236 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
237 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
238 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
241 static int at803x_set_wol(struct phy_device *phydev,
244 struct net_device *ndev = phydev->attached_dev;
264 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
267 value = phy_read(phydev, AT803X_INTR_ENABLE);
269 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
272 value = phy_read(phydev, AT803X_INTR_STATUS);
274 value = phy_read(phydev, AT803X_INTR_ENABLE);
276 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
279 value = phy_read(phydev, AT803X_INTR_STATUS);
285 static void at803x_get_wol(struct phy_device *phydev,
293 value = phy_read(phydev, AT803X_INTR_ENABLE);
298 static int at803x_suspend(struct phy_device *phydev)
303 value = phy_read(phydev, AT803X_INTR_ENABLE);
311 phy_modify(phydev, MII_BMCR, 0, value);
316 static int at803x_resume(struct phy_device *phydev)
318 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
324 struct phy_device *phydev = rdev_get_drvdata(rdev);
327 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
330 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
336 struct phy_device *phydev = rdev_get_drvdata(rdev);
339 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
380 static int at8031_register_regulators(struct phy_device *phydev)
382 struct at803x_priv *priv = phydev->priv;
383 struct device *dev = &phydev->mdio.dev;
387 config.driver_data = phydev;
391 phydev_err(phydev, "failed to register VDDIO regulator\n");
397 phydev_err(phydev, "failed to register VDDH regulator\n");
404 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
406 return (phydev->phy_id & phydev->drv->phy_id_mask)
407 == (phy_id & phydev->drv->phy_id_mask);
410 static int at803x_parse_dt(struct phy_device *phydev)
412 struct device_node *node = phydev->mdio.dev.of_node;
413 struct at803x_priv *priv = phydev->priv;
437 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
455 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
456 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
476 phydev_err(phydev, "invalid qca,clk-out-strength\n");
484 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
488 ret = at8031_register_regulators(phydev);
492 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
495 phydev_err(phydev, "failed to get VDDIO regulator\n");
507 static int at803x_probe(struct phy_device *phydev)
509 struct device *dev = &phydev->mdio.dev;
516 phydev->priv = priv;
518 return at803x_parse_dt(phydev);
521 static void at803x_remove(struct phy_device *phydev)
523 struct at803x_priv *priv = phydev->priv;
529 static int at803x_clk_out_config(struct phy_device *phydev)
531 struct at803x_priv *priv = phydev->priv;
537 val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M);
544 return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val);
547 static int at8031_pll_config(struct phy_device *phydev)
549 struct at803x_priv *priv = phydev->priv;
555 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
558 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
562 static int at803x_config_init(struct phy_device *phydev)
571 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
572 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
573 ret = at803x_enable_rx_delay(phydev);
575 ret = at803x_disable_rx_delay(phydev);
579 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
580 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
581 ret = at803x_enable_tx_delay(phydev);
583 ret = at803x_disable_tx_delay(phydev);
587 ret = at803x_clk_out_config(phydev);
591 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
592 ret = at8031_pll_config(phydev);
600 static int at803x_ack_interrupt(struct phy_device *phydev)
604 err = phy_read(phydev, AT803X_INTR_STATUS);
609 static int at803x_config_intr(struct phy_device *phydev)
614 value = phy_read(phydev, AT803X_INTR_ENABLE);
616 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
623 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
626 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
631 static void at803x_link_change_notify(struct phy_device *phydev)
640 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
643 at803x_context_save(phydev, &context);
645 phy_device_reset(phydev, 1);
647 phy_device_reset(phydev, 0);
650 at803x_context_restore(phydev, &context);
652 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
656 static int at803x_aneg_done(struct phy_device *phydev)
660 int aneg_done = genphy_aneg_done(phydev);
668 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
673 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
676 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
677 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
681 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
686 static int at803x_read_status(struct phy_device *phydev)
688 int ss, err, old_link = phydev->link;
691 err = genphy_update_link(phydev);
696 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
699 phydev->speed = SPEED_UNKNOWN;
700 phydev->duplex = DUPLEX_UNKNOWN;
701 phydev->pause = 0;
702 phydev->asym_pause = 0;
704 err = genphy_read_lpa(phydev);
712 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
719 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
725 phydev->speed = SPEED_10;
728 phydev->speed = SPEED_100;
731 phydev->speed = SPEED_1000;
735 phydev->duplex = DUPLEX_FULL;
737 phydev->duplex = DUPLEX_HALF;
740 phydev->mdix = ETH_TP_MDI_X;
742 phydev->mdix = ETH_TP_MDI;
746 phydev->mdix_ctrl = ETH_TP_MDI;
749 phydev->mdix_ctrl = ETH_TP_MDI_X;
752 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
757 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
758 phy_resolve_aneg_pause(phydev);
763 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
781 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
786 static int at803x_config_aneg(struct phy_device *phydev)
790 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
799 ret = genphy_soft_reset(phydev);
804 return genphy_config_aneg(phydev);
807 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
811 val = phy_read(phydev, AT803X_SMART_SPEED);
823 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
847 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
854 ret = phy_init_hw(phydev);
859 static int at803x_get_tunable(struct phy_device *phydev,
864 return at803x_get_downshift(phydev, data);
870 static int at803x_set_tunable(struct phy_device *phydev,
875 return at803x_set_downshift(phydev, *(const u8 *)data);
936 static int at803x_cdt_start(struct phy_device *phydev, int pair)
943 return phy_write(phydev, AT803X_CDT, cdt);
946 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
951 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
958 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
968 ret = at803x_cdt_start(phydev, pair);
972 ret = at803x_cdt_wait_for_completion(phydev);
976 val = phy_read(phydev, AT803X_CDT_STATUS);
983 ethnl_cable_test_result(phydev, ethtool_pair[pair],
987 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
993 static int at803x_cable_test_get_status(struct phy_device *phydev,
1000 if (phydev->phy_id == ATH9331_PHY_ID ||
1001 phydev->phy_id == ATH8032_PHY_ID)
1017 ret = at803x_cable_test_one_pair(phydev, pair);
1032 static int at803x_cable_test_start(struct phy_device *phydev)
1038 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1039 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1040 if (phydev->phy_id != ATH9331_PHY_ID &&
1041 phydev->phy_id != ATH8032_PHY_ID)
1042 phy_write(phydev, MII_CTRL1000, 0);