Lines Matching defs:phydev
160 static int aqr107_get_sset_count(struct phy_device *phydev)
165 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
174 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
182 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
188 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
198 static void aqr107_get_stats(struct phy_device *phydev,
201 struct aqr107_priv *priv = phydev->priv;
206 val = aqr107_get_stat(phydev, i);
208 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
217 static int aqr_config_aneg(struct phy_device *phydev)
223 if (phydev->autoneg == AUTONEG_DISABLE)
224 return genphy_c45_pma_setup_forced(phydev);
226 ret = genphy_c45_an_config_aneg(phydev);
237 phydev->advertising))
241 phydev->advertising))
246 phydev->advertising))
250 phydev->advertising))
253 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
263 return genphy_c45_check_and_restart_aneg(phydev, changed);
266 static int aqr_config_intr(struct phy_device *phydev)
268 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
271 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
276 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
281 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
286 static int aqr_ack_interrupt(struct phy_device *phydev)
290 reg = phy_read_mmd(phydev, MDIO_MMD_AN,
295 static int aqr_read_status(struct phy_device *phydev)
299 if (phydev->autoneg == AUTONEG_ENABLE) {
300 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
305 phydev->lp_advertising,
308 phydev->lp_advertising,
312 return genphy_c45_read_status(phydev);
315 static int aqr107_read_rate(struct phy_device *phydev)
319 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
325 phydev->speed = SPEED_10;
328 phydev->speed = SPEED_100;
331 phydev->speed = SPEED_1000;
334 phydev->speed = SPEED_2500;
337 phydev->speed = SPEED_5000;
340 phydev->speed = SPEED_10000;
343 phydev->speed = SPEED_UNKNOWN;
348 phydev->duplex = DUPLEX_FULL;
350 phydev->duplex = DUPLEX_HALF;
355 static int aqr107_read_status(struct phy_device *phydev)
359 ret = aqr_read_status(phydev);
363 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
366 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
372 phydev->interface = PHY_INTERFACE_MODE_10GKR;
375 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
378 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
381 phydev->interface = PHY_INTERFACE_MODE_SGMII;
384 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
387 phydev->interface = PHY_INTERFACE_MODE_NA;
392 return aqr107_read_rate(phydev);
395 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
399 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
411 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
423 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
428 static int aqr107_get_tunable(struct phy_device *phydev,
433 return aqr107_get_downshift(phydev, data);
439 static int aqr107_set_tunable(struct phy_device *phydev,
444 return aqr107_set_downshift(phydev, *(const u8 *)data);
457 static int aqr107_wait_reset_complete(struct phy_device *phydev)
461 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
466 static void aqr107_chip_info(struct phy_device *phydev)
471 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
478 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
485 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
489 static int aqr107_config_init(struct phy_device *phydev)
494 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
495 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
496 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
497 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
498 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
499 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
502 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
505 ret = aqr107_wait_reset_complete(phydev);
507 aqr107_chip_info(phydev);
509 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
512 static int aqcs109_config_init(struct phy_device *phydev)
517 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
518 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
521 ret = aqr107_wait_reset_complete(phydev);
523 aqr107_chip_info(phydev);
529 ret = phy_set_max_speed(phydev, SPEED_2500);
533 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
536 static void aqr107_link_change_notify(struct phy_device *phydev)
542 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
545 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
553 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
560 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
566 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
572 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
578 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
581 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
592 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
598 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
605 static int aqr107_suspend(struct phy_device *phydev)
609 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
614 return aqr107_wait_processor_intensive_op(phydev);
617 static int aqr107_resume(struct phy_device *phydev)
621 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
626 return aqr107_wait_processor_intensive_op(phydev);
629 static int aqr107_probe(struct phy_device *phydev)
631 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
633 if (!phydev->priv)
636 return aqr_hwmon_probe(phydev);