Lines Matching defs:phydev
195 static u32 adin_get_reg_value(struct phy_device *phydev,
200 struct device *dev = &phydev->mdio.dev;
209 phydev_warn(phydev,
218 static int adin_config_rgmii_mode(struct phy_device *phydev)
223 if (!phy_interface_is_rgmii(phydev))
224 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
228 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
234 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
235 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
238 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
248 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
251 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
260 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
264 static int adin_config_rmii_mode(struct phy_device *phydev)
269 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
270 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
274 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
280 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
287 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
291 static int adin_get_downshift(struct phy_device *phydev, u8 *data)
295 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
299 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
311 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
317 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
326 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
332 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
336 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
340 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
357 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
362 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
379 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
384 static int adin_get_tunable(struct phy_device *phydev,
389 return adin_get_downshift(phydev, data);
391 return adin_get_edpd(phydev, data);
397 static int adin_set_tunable(struct phy_device *phydev,
402 return adin_set_downshift(phydev, *(const u8 *)data);
404 return adin_set_edpd(phydev, *(const u16 *)data);
410 static int adin_config_init(struct phy_device *phydev)
414 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
416 rc = adin_config_rgmii_mode(phydev);
420 rc = adin_config_rmii_mode(phydev);
424 rc = adin_set_downshift(phydev, 4);
428 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
432 phydev_dbg(phydev, "PHY is using mode '%s'\n",
433 phy_modes(phydev->interface));
438 static int adin_phy_ack_intr(struct phy_device *phydev)
441 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
446 static int adin_phy_config_intr(struct phy_device *phydev)
448 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
449 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
452 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
456 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
471 phydev_err(phydev,
478 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
480 struct mii_bus *bus = phydev->mdio.bus;
481 int phy_addr = phydev->mdio.addr;
485 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
497 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
500 struct mii_bus *bus = phydev->mdio.bus;
501 int phy_addr = phydev->mdio.addr;
505 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
517 static int adin_config_mdix(struct phy_device *phydev)
524 switch (phydev->mdix_ctrl) {
537 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
551 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
554 static int adin_config_aneg(struct phy_device *phydev)
558 ret = adin_config_mdix(phydev);
562 return genphy_config_aneg(phydev);
565 static int adin_mdix_update(struct phy_device *phydev)
571 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
581 phydev->mdix = ETH_TP_MDI_X;
583 phydev->mdix = ETH_TP_MDI;
592 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
599 phydev->mdix = ETH_TP_MDI_X;
601 phydev->mdix = ETH_TP_MDI;
606 static int adin_read_status(struct phy_device *phydev)
610 ret = adin_mdix_update(phydev);
614 return genphy_read_status(phydev);
617 static int adin_soft_reset(struct phy_device *phydev)
622 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
631 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
637 static int adin_get_sset_count(struct phy_device *phydev)
642 static void adin_get_strings(struct phy_device *phydev, u8 *data)
652 static int adin_read_mmd_stat_regs(struct phy_device *phydev,
658 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
667 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
677 static u64 adin_get_stat(struct phy_device *phydev, int i)
680 struct adin_priv *priv = phydev->priv;
685 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
689 ret = phy_read(phydev, stat->reg1);
700 static void adin_get_stats(struct phy_device *phydev,
706 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
711 data[i] = adin_get_stat(phydev, i);
714 static int adin_probe(struct phy_device *phydev)
716 struct device *dev = &phydev->mdio.dev;
723 phydev->priv = priv;