Lines Matching refs:devrec
542 struct mrf24j40 *devrec = context;
543 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
553 devrec->tx_post_msg.complete = NULL;
554 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
555 devrec->tx_post_buf[1] = val;
557 ret = spi_async(devrec->spi, &devrec->tx_post_msg);
559 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
565 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
573 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
578 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
579 devrec->tx_hdr_buf[1] = cmd & 0xff;
580 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
581 devrec->tx_len_buf[1] = length; /* Total length */
582 devrec->tx_buf_trx.tx_buf = data;
583 devrec->tx_buf_trx.len = length;
585 ret = spi_async(devrec->spi, &devrec->tx_msg);
587 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
594 struct mrf24j40 *devrec = hw->priv;
596 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
597 devrec->tx_skb = skb;
599 return write_tx_buf(devrec, 0x000, skb->data, skb->len);
612 struct mrf24j40 *devrec = hw->priv;
614 dev_dbg(printdev(devrec), "start\n");
617 return regmap_update_bits(devrec->regmap_short, REG_INTCON,
623 struct mrf24j40 *devrec = hw->priv;
625 dev_dbg(printdev(devrec), "stop\n");
628 regmap_update_bits(devrec->regmap_short, REG_INTCON,
634 struct mrf24j40 *devrec = hw->priv;
638 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
646 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
652 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
657 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
668 struct mrf24j40 *devrec = hw->priv;
670 dev_dbg(printdev(devrec), "filter\n");
679 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
680 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
681 dev_dbg(printdev(devrec),
691 regmap_write(devrec->regmap_short, REG_EADR0 + i,
708 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
709 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
711 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
723 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
732 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
739 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
744 devrec->rx_msg.complete = NULL;
745 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
746 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
747 ret = spi_async(devrec->spi, &devrec->rx_msg);
749 dev_err(printdev(devrec), "failed to unlock rx buffer\n");
754 struct mrf24j40 *devrec = context;
755 u8 len = devrec->rx_buf[2];
759 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
760 mrf24j40_handle_rx_read_buf_unlock(devrec);
764 dev_err(printdev(devrec), "failed to allocate skb\n");
769 ieee802154_rx_irqsafe(devrec->hw, skb, 0);
775 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
781 struct mrf24j40 *devrec = context;
786 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
787 devrec->rx_buf[2] = IEEE802154_MTU;
790 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
791 devrec->rx_addr_buf[1] = cmd & 0xff;
792 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
793 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
795 dev_err(printdev(devrec), "failed to read rx buffer\n");
796 mrf24j40_handle_rx_read_buf_unlock(devrec);
802 struct mrf24j40 *devrec = context;
807 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
808 devrec->rx_trx.len = 3;
810 devrec->rx_buf[0] = cmd >> 8 & 0xff;
811 devrec->rx_buf[1] = cmd & 0xff;
813 ret = spi_async(devrec->spi, &devrec->rx_msg);
815 dev_err(printdev(devrec), "failed to read rx buffer length\n");
816 mrf24j40_handle_rx_read_buf_unlock(devrec);
820 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
825 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
826 devrec->rx_trx.len = 2;
827 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
828 devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
830 return spi_async(devrec->spi, &devrec->rx_msg);
837 struct mrf24j40 *devrec = hw->priv;
845 return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
853 struct mrf24j40 *devrec = hw->priv;
877 return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
912 struct mrf24j40 *devrec = hw->priv;
917 return regmap_write(devrec->regmap_short, REG_CCAEDTH,
932 struct mrf24j40 *devrec = hw->priv;
981 return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
987 struct mrf24j40 *devrec = hw->priv;
992 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
997 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
1022 struct mrf24j40 *devrec = context;
1023 u8 intstat = devrec->irq_buf[1];
1025 enable_irq(devrec->spi->irq);
1029 regmap_write_async(devrec->regmap_short, REG_SECCON0,
1034 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
1038 mrf24j40_handle_rx(devrec);
1043 struct mrf24j40 *devrec = data;
1048 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
1049 devrec->irq_buf[1] = 0;
1052 ret = spi_async(devrec->spi, &devrec->irq_msg);
1061 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
1068 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
1072 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
1076 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
1080 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
1084 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
1088 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
1092 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
1096 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
1100 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
1104 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
1108 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
1112 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
1116 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
1120 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
1124 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
1131 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
1135 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
1139 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
1143 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
1147 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
1152 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
1155 irq_type = irq_get_trigger_type(devrec->spi->irq);
1158 dev_warn(&devrec->spi->dev,
1164 ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
1181 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1183 spi_message_init(&devrec->tx_msg);
1184 devrec->tx_msg.context = devrec;
1185 devrec->tx_msg.complete = write_tx_buf_complete;
1186 devrec->tx_hdr_trx.len = 2;
1187 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1188 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1189 devrec->tx_len_trx.len = 2;
1190 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1191 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1192 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1194 spi_message_init(&devrec->tx_post_msg);
1195 devrec->tx_post_msg.context = devrec;
1196 devrec->tx_post_trx.len = 2;
1197 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1198 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1202 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
1204 spi_message_init(&devrec->rx_msg);
1205 devrec->rx_msg.context = devrec;
1206 devrec->rx_trx.len = 2;
1207 devrec->rx_trx.tx_buf = devrec->rx_buf;
1208 devrec->rx_trx.rx_buf = devrec->rx_buf;
1209 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1211 spi_message_init(&devrec->rx_buf_msg);
1212 devrec->rx_buf_msg.context = devrec;
1213 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1214 devrec->rx_addr_trx.len = 2;
1215 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1216 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1217 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1218 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1219 devrec->rx_lqi_trx.len = 2;
1220 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1221 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1225 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1227 spi_message_init(&devrec->irq_msg);
1228 devrec->irq_msg.context = devrec;
1229 devrec->irq_msg.complete = mrf24j40_intstat_complete;
1230 devrec->irq_trx.len = 2;
1231 devrec->irq_trx.tx_buf = devrec->irq_buf;
1232 devrec->irq_trx.rx_buf = devrec->irq_buf;
1233 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1236 static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
1238 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1239 devrec->hw->phy->current_channel = 11;
1242 devrec->hw->phy->supported.max_minbe = 3;
1246 devrec->hw->phy->supported.min_maxbe = 5;
1247 devrec->hw->phy->supported.max_maxbe = 5;
1249 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
1250 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1253 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
1255 devrec->hw->phy->cca_ed_level = -6900;
1256 devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
1257 devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
1259 switch (spi_get_device_id(devrec->spi)->driver_data) {
1262 devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
1263 devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
1264 devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
1275 struct mrf24j40 *devrec;
1281 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1285 devrec = hw->priv;
1286 devrec->spi = spi;
1287 spi_set_drvdata(spi, devrec);
1288 devrec->hw = hw;
1289 devrec->hw->parent = &spi->dev;
1290 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1291 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1295 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
1298 mrf24j40_setup_tx_spi_messages(devrec);
1299 mrf24j40_setup_rx_spi_messages(devrec);
1300 mrf24j40_setup_irq_spi_messages(devrec);
1302 devrec->regmap_short = devm_regmap_init_spi(spi,
1304 if (IS_ERR(devrec->regmap_short)) {
1305 ret = PTR_ERR(devrec->regmap_short);
1311 devrec->regmap_long = devm_regmap_init(&spi->dev,
1314 if (IS_ERR(devrec->regmap_long)) {
1315 ret = PTR_ERR(devrec->regmap_long);
1328 ret = mrf24j40_hw_init(devrec);
1332 mrf24j40_phy_setup(devrec);
1340 irq_type, dev_name(&spi->dev), devrec);
1342 dev_err(printdev(devrec), "Unable to get IRQ");
1346 dev_dbg(printdev(devrec), "registered mrf24j40\n");
1347 ret = ieee802154_register_hw(devrec->hw);
1354 ieee802154_free_hw(devrec->hw);
1361 struct mrf24j40 *devrec = spi_get_drvdata(spi);
1363 dev_dbg(printdev(devrec), "remove\n");
1365 ieee802154_unregister_hw(devrec->hw);
1366 ieee802154_free_hw(devrec->hw);