Lines Matching refs:lp
447 struct mcr20a_local *lp = context;
450 dev_dbg(printdev(lp), "%s\n", __func__);
452 lp->reg_msg.complete = NULL;
453 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
454 lp->reg_data[0] = MCR20A_XCVSEQ_TX;
455 lp->reg_xfer_data.len = 1;
457 ret = spi_async(lp->spi, &lp->reg_msg);
459 dev_err(printdev(lp), "failed to set SEQ TX\n");
465 struct mcr20a_local *lp = hw->priv;
467 dev_dbg(printdev(lp), "%s\n", __func__);
469 lp->tx_skb = skb;
474 lp->is_tx = 1;
476 lp->reg_msg.complete = NULL;
477 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
478 lp->reg_data[0] = MCR20A_XCVSEQ_IDLE;
479 lp->reg_xfer_data.len = 1;
481 return spi_async(lp->spi, &lp->reg_msg);
495 struct mcr20a_local *lp = hw->priv;
498 dev_dbg(printdev(lp), "%s\n", __func__);
501 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]);
504 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00);
507 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB,
518 struct mcr20a_local *lp = hw->priv;
521 dev_dbg(printdev(lp), "%s\n", __func__);
524 dev_dbg(printdev(lp), "no slotted operation\n");
525 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
531 enable_irq(lp->spi->irq);
534 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2,
540 dev_dbg(printdev(lp), "start the RX sequence\n");
541 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
552 struct mcr20a_local *lp = hw->priv;
554 dev_dbg(printdev(lp), "%s\n", __func__);
557 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
561 disable_irq(lp->spi->irq);
569 struct mcr20a_local *lp = hw->priv;
571 dev_dbg(printdev(lp), "%s\n", __func__);
576 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr);
577 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8);
583 regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan);
584 regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8);
592 regmap_write(lp->regmap_iar,
598 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
601 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
619 struct mcr20a_local *lp = hw->priv;
622 dev_dbg(printdev(lp), "%s(%d)\n", __func__, mbm);
624 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
625 if (lp->hw->phy->supported.tx_powers[i] == mbm)
626 return regmap_write(lp->regmap_dar, DAR_PA_PWR,
640 struct mcr20a_local *lp = hw->priv;
645 dev_dbg(printdev(lp), "%s\n", __func__);
672 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
680 ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL,
684 ret = regmap_update_bits(lp->regmap_iar,
699 struct mcr20a_local *lp = hw->priv;
702 dev_dbg(printdev(lp), "%s\n", __func__);
706 return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i);
715 struct mcr20a_local *lp = hw->priv;
719 dev_dbg(printdev(lp), "%s(%d)\n", __func__, on);
727 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
733 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
738 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
743 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
770 mcr20a_request_rx(struct mcr20a_local *lp)
772 dev_dbg(printdev(lp), "%s\n", __func__);
775 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
784 struct mcr20a_local *lp = context;
785 u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
788 dev_dbg(printdev(lp), "%s\n", __func__);
790 dev_dbg(printdev(lp), "RX is done\n");
793 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
803 __skb_put_data(skb, lp->rx_buf, len);
804 ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]);
807 lp->rx_buf, len, 0);
808 pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]);
811 mcr20a_request_rx(lp);
817 struct mcr20a_local *lp = context;
821 dev_dbg(printdev(lp), "%s\n", __func__);
824 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
825 dev_dbg(printdev(lp), "frame len : %d\n", len);
828 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
829 lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF;
830 lp->rx_xfer_buf.len = len;
832 ret = spi_async(lp->spi, &lp->rx_buf_msg);
834 dev_err(printdev(lp), "failed to read rx buffer length\n");
838 mcr20a_handle_rx(struct mcr20a_local *lp)
840 dev_dbg(printdev(lp), "%s\n", __func__);
841 lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete;
842 lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN);
843 lp->reg_xfer_data.len = 1;
845 return spi_async(lp->spi, &lp->reg_msg);
849 mcr20a_handle_tx_complete(struct mcr20a_local *lp)
851 dev_dbg(printdev(lp), "%s\n", __func__);
853 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
855 return mcr20a_request_rx(lp);
859 mcr20a_handle_tx(struct mcr20a_local *lp)
863 dev_dbg(printdev(lp), "%s\n", __func__);
866 lp->tx_header[0] = MCR20A_BURST_WRITE_PACKET_BUF;
868 lp->tx_len[0] = lp->tx_skb->len + 2;
869 lp->tx_xfer_buf.tx_buf = lp->tx_skb->data;
871 lp->tx_xfer_buf.len = lp->tx_skb->len + 1;
873 ret = spi_async(lp->spi, &lp->tx_buf_msg);
875 dev_err(printdev(lp), "SPI write Failed for TX buf\n");
885 struct mcr20a_local *lp = context;
886 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK;
888 dev_dbg(printdev(lp), "%s\n", __func__);
890 enable_irq(lp->spi->irq);
892 dev_dbg(printdev(lp), "IRQ STA1 (%02x) STA2 (%02x)\n",
893 lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]);
898 if (lp->is_tx) {
899 lp->is_tx = 0;
900 dev_dbg(printdev(lp), "TX is done. No ACK\n");
901 mcr20a_handle_tx_complete(lp);
906 dev_dbg(printdev(lp), "RX is starting\n");
907 mcr20a_handle_rx(lp);
910 if (lp->is_tx) {
912 lp->is_tx = 0;
913 dev_dbg(printdev(lp), "TX is done. Get ACK\n");
914 mcr20a_handle_tx_complete(lp);
917 dev_dbg(printdev(lp), "RX is starting\n");
918 mcr20a_handle_rx(lp);
922 if (lp->is_tx) {
923 dev_dbg(printdev(lp), "TX is starting\n");
924 mcr20a_handle_tx(lp);
926 dev_dbg(printdev(lp), "MCR20A is stop\n");
935 struct mcr20a_local *lp = context;
937 dev_dbg(printdev(lp), "%s\n", __func__);
938 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
941 lp->reg_msg.complete = mcr20a_irq_clean_complete;
942 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1);
943 memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM);
944 lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM;
946 ret = spi_async(lp->spi, &lp->reg_msg);
949 dev_err(printdev(lp), "failed to clean irq status\n");
954 struct mcr20a_local *lp = data;
959 lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1);
961 ret = spi_async(lp->spi, &lp->irq_msg);
970 static void mcr20a_hw_setup(struct mcr20a_local *lp)
973 struct ieee802154_hw *hw = lp->hw;
974 struct wpan_phy *phy = lp->hw->phy;
976 dev_dbg(printdev(lp), "%s\n", __func__);
1017 mcr20a_setup_tx_spi_messages(struct mcr20a_local *lp)
1019 spi_message_init(&lp->tx_buf_msg);
1020 lp->tx_buf_msg.context = lp;
1021 lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete;
1023 lp->tx_xfer_header.len = 1;
1024 lp->tx_xfer_header.tx_buf = lp->tx_header;
1026 lp->tx_xfer_len.len = 1;
1027 lp->tx_xfer_len.tx_buf = lp->tx_len;
1029 spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg);
1030 spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg);
1031 spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg);
1035 mcr20a_setup_rx_spi_messages(struct mcr20a_local *lp)
1037 spi_message_init(&lp->reg_msg);
1038 lp->reg_msg.context = lp;
1040 lp->reg_xfer_cmd.len = 1;
1041 lp->reg_xfer_cmd.tx_buf = lp->reg_cmd;
1042 lp->reg_xfer_cmd.rx_buf = lp->reg_cmd;
1044 lp->reg_xfer_data.rx_buf = lp->reg_data;
1045 lp->reg_xfer_data.tx_buf = lp->reg_data;
1047 spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg);
1048 spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg);
1050 spi_message_init(&lp->rx_buf_msg);
1051 lp->rx_buf_msg.context = lp;
1052 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
1053 lp->rx_xfer_header.len = 1;
1054 lp->rx_xfer_header.tx_buf = lp->rx_header;
1055 lp->rx_xfer_header.rx_buf = lp->rx_header;
1057 lp->rx_xfer_buf.rx_buf = lp->rx_buf;
1059 lp->rx_xfer_lqi.len = 1;
1060 lp->rx_xfer_lqi.rx_buf = lp->rx_lqi;
1062 spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg);
1063 spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg);
1064 spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg);
1068 mcr20a_setup_irq_spi_messages(struct mcr20a_local *lp)
1070 spi_message_init(&lp->irq_msg);
1071 lp->irq_msg.context = lp;
1072 lp->irq_msg.complete = mcr20a_irq_status_complete;
1073 lp->irq_xfer_header.len = 1;
1074 lp->irq_xfer_header.tx_buf = lp->irq_header;
1075 lp->irq_xfer_header.rx_buf = lp->irq_header;
1077 lp->irq_xfer_data.len = MCR20A_IRQSTS_NUM;
1078 lp->irq_xfer_data.rx_buf = lp->irq_data;
1080 spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg);
1081 spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg);
1085 mcr20a_phy_init(struct mcr20a_local *lp)
1091 dev_dbg(printdev(lp), "%s\n", __func__);
1094 ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02);
1101 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF);
1106 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2,
1113 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF);
1118 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
1122 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF);
1127 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3,
1136 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL,
1144 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
1152 dev_info(printdev(lp), "MCR20A DAR overwrites version: 0x%02x\n",
1156 ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER,
1162 ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites,
1168 dev_dbg(printdev(lp), "clear HW indirect queue\n");
1174 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg);
1181 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg);
1191 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg);
1196 ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B);
1201 ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05);
1206 ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES,
1213 ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL,
1228 struct mcr20a_local *lp;
1256 hw = ieee802154_alloc_hw(sizeof(*lp), &mcr20a_hw_ops);
1263 lp = hw->priv;
1264 lp->hw = hw;
1265 lp->spi = spi;
1272 lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL);
1274 if (!lp->buf) {
1279 mcr20a_setup_tx_spi_messages(lp);
1280 mcr20a_setup_rx_spi_messages(lp);
1281 mcr20a_setup_irq_spi_messages(lp);
1284 lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap);
1285 if (IS_ERR(lp->regmap_dar)) {
1286 ret = PTR_ERR(lp->regmap_dar);
1292 lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap);
1293 if (IS_ERR(lp->regmap_iar)) {
1294 ret = PTR_ERR(lp->regmap_iar);
1299 mcr20a_hw_setup(lp);
1301 spi_set_drvdata(spi, lp);
1303 ret = mcr20a_phy_init(lp);
1314 irq_type, dev_name(&spi->dev), lp);
1333 ieee802154_free_hw(lp->hw);
1340 struct mcr20a_local *lp = spi_get_drvdata(spi);
1344 ieee802154_unregister_hw(lp->hw);
1345 ieee802154_free_hw(lp->hw);