Lines Matching refs:cas_ctl
722 static void ca8210_rx_done(struct cas_control *cas_ctl)
727 struct ca8210_priv *priv = cas_ctl->priv;
729 buf = cas_ctl->tx_in_buf;
842 struct cas_control *cas_ctl = context;
843 struct ca8210_priv *priv = cas_ctl->priv;
849 cas_ctl->tx_in_buf[0] == SPI_NACK ||
850 (cas_ctl->tx_in_buf[0] == SPI_IDLE &&
851 cas_ctl->tx_in_buf[1] == SPI_NACK)
855 if (cas_ctl->tx_buf[0] == SPI_IDLE) {
860 kfree(cas_ctl);
865 kfree(cas_ctl);
869 memcpy(retry_buffer, cas_ctl->tx_buf, CA8210_SPI_BUF_SIZE);
870 kfree(cas_ctl);
880 cas_ctl->tx_in_buf[0] != SPI_IDLE &&
881 cas_ctl->tx_in_buf[0] != SPI_NACK
888 for (i = 0; i < cas_ctl->tx_in_buf[1] + 2; i++)
892 cas_ctl->tx_in_buf[i]
894 ca8210_rx_done(cas_ctl);
897 kfree(cas_ctl);
917 struct cas_control *cas_ctl;
929 cas_ctl = kzalloc(sizeof(*cas_ctl), GFP_ATOMIC);
930 if (!cas_ctl)
933 cas_ctl->priv = priv;
934 memset(cas_ctl->tx_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
935 memset(cas_ctl->tx_in_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
936 memcpy(cas_ctl->tx_buf, buf, len);
939 dev_dbg(&spi->dev, "%#03x\n", cas_ctl->tx_buf[i]);
941 spi_message_init(&cas_ctl->msg);
943 cas_ctl->transfer.tx_nbits = 1; /* 1 MOSI line */
944 cas_ctl->transfer.rx_nbits = 1; /* 1 MISO line */
945 cas_ctl->transfer.speed_hz = 0; /* Use device setting */
946 cas_ctl->transfer.bits_per_word = 0; /* Use device setting */
947 cas_ctl->transfer.tx_buf = cas_ctl->tx_buf;
948 cas_ctl->transfer.rx_buf = cas_ctl->tx_in_buf;
949 cas_ctl->transfer.delay.value = 0;
950 cas_ctl->transfer.delay.unit = SPI_DELAY_UNIT_USECS;
951 cas_ctl->transfer.cs_change = 0;
952 cas_ctl->transfer.len = sizeof(struct mac_message);
953 cas_ctl->msg.complete = ca8210_spi_transfer_complete;
954 cas_ctl->msg.context = cas_ctl;
957 &cas_ctl->transfer,
958 &cas_ctl->msg
961 status = spi_async(spi, &cas_ctl->msg);