Lines Matching refs:ctrl

279 	OutReg(scc->ctrl, reg, (scc->wreg[reg] = val));
284 OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val));
289 OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val));
359 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
385 Outb(scc->ctrl, RES_Tx_P);
394 Outb(scc->ctrl, RES_Tx_P);
400 OutReg(scc->ctrl, R0, RES_Tx_CRC);
407 Outb(scc->ctrl,RES_EOM_L);
415 Outb(scc->ctrl, RES_Tx_P); /* reset pending int */
437 status = InReg(scc->ctrl,R0);
455 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
498 Outb(scc->ctrl, RES_EXT_INT); /* reset ext/status interrupts */
511 Outb(scc->ctrl,RES_EXT_INT);
571 status = InReg(scc->ctrl,R1); /* read receiver status */
604 Outb(scc->ctrl,ERR_RES);
635 struct scc_ctrl *ctrl;
653 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */
666 ctrl = SCC_ctrl;
667 while (ctrl->chan_A)
669 if (ctrl->irq != chip_irq)
671 ctrl++;
676 for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++)
678 vector=InReg(ctrl->chan_B,R2); /* Read the vector */
702 OutReg(scc->ctrl,R0,RES_H_IUS);
703 ctrl = SCC_ctrl;
705 ctrl++;
744 OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]); /* DPLL source = BRG */
745 OutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]); /* DPLL NRZI mode */
851 OutReg(scc->ctrl, R14, DISDPLL);
864 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD))
874 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
875 Outb(scc->ctrl,RES_EXT_INT); /* must be done twice */
879 scc->status = InReg(scc->ctrl,R0); /* read initial status */
904 Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0));
1253 OutReg(scc->ctrl, R0, RES_Tx_P);
1412 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
1413 Outb(scc->ctrl,RES_EXT_INT);
1444 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
1445 Outb(scc->ctrl,RES_EXT_INT);
1483 if (!scc->ctrl) continue;
1498 Outb(scc->ctrl, 0);
1499 OutReg(scc->ctrl,R9,FHWRES); /* force hardware reset */
1605 Outb(scc->ctrl,0); /* Make sure pointer is written */
1780 SCC_Info[2*Nchips ].ctrl = hwcfg.ctrl_a;
1783 SCC_Info[2*Nchips+1].ctrl = hwcfg.ctrl_b;
1807 SCC_Info[2*Nchips+chan].ctrl);
1819 request_region(SCC_Info[2*Nchips+chan].ctrl, 1, "scc ctrl");
2026 /* dev data ctrl irq clock brand enh vector special option
2037 scc->data, scc->ctrl, scc->irq, scc->clock, scc->brand,
2066 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1));
2068 seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
2071 seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
2117 io_port ctrl;
2132 if ( (ctrl = SCC_ctrl[k].chan_A) )
2134 Outb(ctrl, 0);
2135 OutReg(ctrl,R9,FHWRES); /* force hardware reset */
2149 if (scc->ctrl)
2151 release_region(scc->ctrl, 1);