Lines Matching defs:write_scc
221 static void write_scc(struct scc_priv *priv, int reg, int val);
282 write_scc(&info->priv[0], R9, FHWRES);
451 /* Initialize what is necessary for write_scc and write_scc_data */
485 write_scc(priv, R9, FHWRES | MIE | NV);
488 write_scc(priv, R15, SHDLCE);
503 write_scc(priv, R15, 0);
516 write_scc(priv, R15, CTSIE);
517 write_scc(priv, R0, RES_EXT_INT);
518 write_scc(priv, R1, EXT_INT_ENAB);
534 write_scc(priv, R1, 0);
535 write_scc(priv, R15, 0);
536 write_scc(priv, R0, RES_EXT_INT);
602 write_scc(&info->priv[0], R9, FHWRES);
615 static void write_scc(struct scc_priv *priv, int reg, int val)
749 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
751 write_scc(priv, R4, SDLC | X1CLK);
753 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
755 write_scc(priv, R3, Rx8);
757 write_scc(priv, R5, Tx8);
759 write_scc(priv, R6, 0);
761 write_scc(priv, R7, FLAG);
765 write_scc(priv, R15, SHDLCE);
767 write_scc(priv, R7, AUTOEOM);
768 write_scc(priv, R15, 0);
772 write_scc(priv, R15, SHDLCE);
794 write_scc(priv, R7, AUTOEOM | TXFIFOE);
796 write_scc(priv, R7, AUTOEOM);
798 write_scc(priv, R7, AUTOEOM | RXFIFOH);
800 write_scc(priv, R15, 0);
804 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
809 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
810 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
813 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
815 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
818 write_scc(priv, R14, DTRREQ | BRSRC);
828 write_scc(priv, R11, priv->param.clocks);
847 write_scc(priv, R15, DCDIE);
871 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
946 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
947 write_scc(priv, R15, 0);
983 write_scc(priv, R15, TxUIE);
990 write_scc(priv, R1,
1001 write_scc(priv, R15, TxUIE);
1002 write_scc(priv, R1,
1008 write_scc(priv, R0, RES_EOM_L);
1036 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1042 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1045 write_scc(priv, R0, ERR_RES);
1046 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1053 write_scc(priv, R3, Rx8);
1058 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1074 write_scc(priv, R15, r15 | CTSIE);
1106 write_scc(&info->priv[0], R0, RES_H_IUS);
1161 write_scc(priv, R0, ERR_RES);
1193 write_scc(priv, R0, ERR_RES);
1292 write_scc(priv, R0, RES_Tx_P);
1303 write_scc(priv, R0, RES_EOM_L);
1316 write_scc(priv, R0, RES_EXT_INT);
1338 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1344 write_scc(priv, R0, RES_EXT_INT);
1345 write_scc(priv, R0, RES_EXT_INT);
1357 write_scc(priv, R15, 0);
1375 write_scc(priv, R15, 0);
1383 write_scc(priv, R15, 0);
1405 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1408 write_scc(priv, R15, 0);
1412 write_scc(priv, R15, DCDIE);
1427 write_scc(priv, R5,
1429 write_scc(priv, R15, 0);
1434 write_scc(priv, R15, DCDIE);
1439 write_scc(priv, R15, DCDIE);