Lines Matching refs:outpw
152 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
190 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
191 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
192 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
193 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
199 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
200 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
201 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
202 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
205 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
206 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
207 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
208 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
217 outpw(FM_A(FM_CMDREG2),FM_IRSTQ) ; /* reset transmit queues */
222 outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */
223 outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */
224 outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */
225 outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */
231 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ;
232 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ;
233 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ;
234 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
237 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
238 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
239 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
240 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
256 outpw(FM_A(FM_RPXA1),rbc_ram_addr) ; /* a1-send pointer */
257 outpw(FM_A(FM_WPXA1),rbc_ram_addr) ;
258 outpw(FM_A(FM_SWPXA1),rbc_ram_addr) ;
259 outpw(FM_A(FM_EAA1),rbc_ram_addr) ;
292 outpw(FM_A(FM_TSYNC),(unsigned int) (((-sync_bw) >> 5) & 0xffff) ) ;
332 outpw(FM_A(FM_FCNTR),0) ;
333 outpw(FM_A(FM_LCNTR),0) ;
334 outpw(FM_A(FM_ECNTR),0) ;
351 outpw(FM_A(FM_SAID),my_said) ; /* set short address */
352 outpw(FM_A(FM_LAIL),(unsigned short)((smc->hw.fddi_home_addr.a[4]<<8) +
354 outpw(FM_A(FM_LAIC),(unsigned short)((smc->hw.fddi_home_addr.a[2]<<8) +
356 outpw(FM_A(FM_LAIM),(unsigned short)((smc->hw.fddi_home_addr.a[0]<<8) +
359 outpw(FM_A(FM_SAGP),my_sagp) ; /* set short group address */
361 outpw(FM_A(FM_LAGL),(unsigned short)((smc->hw.fp.group_addr.a[4]<<8) +
363 outpw(FM_A(FM_LAGC),(unsigned short)((smc->hw.fp.group_addr.a[2]<<8) +
365 outpw(FM_A(FM_LAGM),(unsigned short)((smc->hw.fp.group_addr.a[0]<<8) +
369 outpw(FM_A(FM_TREQ1),(unsigned short)(t_requ>>16)) ;
370 outpw(FM_A(FM_TREQ0),(unsigned short)t_requ) ;
406 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ;
412 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
455 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
458 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ;
488 outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ;
503 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ;
522 outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ;
524 outpw(FM_A(FM_WPXSF),0) ;
525 outpw(FM_A(FM_RPXSF),0) ;
533 outpw(FM_A(FM_CMDREG1),FM_ICLLR) ; /* clear receive lock */
538 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
539 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
545 outpw(FM_A(FM_IMSK1U),(unsigned short)~mac_imsk1u);
546 outpw(FM_A(FM_IMSK1L),(unsigned short)~mac_imsk1l);
547 outpw(FM_A(FM_IMSK2U),(unsigned short)~mac_imsk2u);
548 outpw(FM_A(FM_IMSK2L),(unsigned short)~mac_imsk2l);
549 outpw(FM_A(FM_IMSK3U),(unsigned short)~mac_imsk3u);
550 outpw(FM_A(FM_IMSK3L),(unsigned short)~mac_imsk3l);
590 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMS)) ;
593 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMA0)) ;
625 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMS)) ;
628 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMA0)) ;
636 outpw(FM_A(FM_IMSK1U),MW) ;
637 outpw(FM_A(FM_IMSK1L),MW) ;
638 outpw(FM_A(FM_IMSK2U),MW) ;
639 outpw(FM_A(FM_IMSK2L),MW) ;
640 outpw(FM_A(FM_IMSK3U),MW) ;
641 outpw(FM_A(FM_IMSK3L),MW) ;
657 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;
792 outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ;
823 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;/* abort current transmit activity */
895 outpw(FM_A(FM_MDREG1),FM_MINIT) ; /* FORMAC+ init mode */
897 outpw(FM_A(FM_MDREG1),FM_MMEMACT) ; /* FORMAC+ memory activ mode */
899 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
925 outpw(FM_A(FM_FRMTHR),14<<12) ; /* switch on */
928 outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ;
929 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
930 outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ;
931 outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ;
944 outpw(FM_A(FM_TMAX),(u_short)t_max) ;
948 outpw(FM_A(FM_TVX), (u_short) (- US2BCLK(52))/255 & MB) ;
950 outpw(FM_A(FM_TVX),
954 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
955 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
956 outpw(FM_A(FM_CMDREG1),FM_ICLLR); /* clear receive lock */
959 outpw(FM_A(FM_UNLCKDLY),(0xff|(0xff<<8))) ;
1009 outpw(FM_A(FM_IMSK2U),~(mac_imsk2u | mac_beacon_imsk2u)) ;
1201 outpw(FM_A(FM_AFCMD),FM_IINV_CAM) ;
1208 outpw(FM_A(FM_AFMASK2),0xffff) ;
1209 outpw(FM_A(FM_AFMASK1),(u_short) ~((fu[0] << 8) + fu[1])) ;
1210 outpw(FM_A(FM_AFMASK0),(u_short) ~((fu[2] << 8) + fu[3])) ;
1211 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1212 outpw(FM_A(FM_AFCOMP2), 0xc000) ;
1213 outpw(FM_A(FM_AFCOMP1), 0x0000) ;
1214 outpw(FM_A(FM_AFCOMP0), 0x0000) ;
1215 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1221 outpw(FM_A(FM_AFMASK0),0xffff) ;
1222 outpw(FM_A(FM_AFMASK1),0xffff) ;
1223 outpw(FM_A(FM_AFMASK2),0xffff) ;
1224 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1233 outpw(FM_A(FM_AFCOMP2),
1235 outpw(FM_A(FM_AFCOMP1),
1237 outpw(FM_A(FM_AFCOMP0),
1239 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1326 outpw(ADDR(B2_RTM_CRTL),TIM_CL_IRQ) ; /* clear IRQ */
1328 outpw(FM_A(FM_CMDREG1),FM_ICL) ; /* force claim */
1334 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable RTM monitoring */
1340 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable IRQ */