Lines Matching defs:queue
188 * initialize the pointer for receive queue 1
196 * initialize the pointer for receive queue 2
220 * initialize the pointer for asynchronous transmit queue
228 * initialize the pointer for synchronous transmit queue
270 struct s_smt_rx_queue *queue ;
273 * init all tx data structures for receive queue 1
275 smc->hw.fp.rx[QUEUE_R1] = queue = &smc->hw.fp.rx_q[QUEUE_R1] ;
276 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ;
277 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R1_DA) ;
280 * init all tx data structures for receive queue 2
282 smc->hw.fp.rx[QUEUE_R2] = queue = &smc->hw.fp.rx_q[QUEUE_R2] ;
283 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;
284 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R2_DA) ;
300 struct s_smt_tx_queue *queue ;
303 * init all tx data structures for the synchronous queue
305 smc->hw.fp.tx[QUEUE_S] = queue = &smc->hw.fp.tx_q[QUEUE_S] ;
306 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;
307 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XS_DA) ;
314 * init all tx data structures for the asynchronous queue 0
316 smc->hw.fp.tx[QUEUE_A0] = queue = &smc->hw.fp.tx_q[QUEUE_A0] ;
317 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;
318 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XA_DA) ;
444 * enable FORMAC to send endless queue of directed beacon
521 /* end of claim/beacon queue */
559 void enable_tx_irq(smc, queue)
561 u_short queue ;
565 interrupt of the queue.
567 Para queue = QUEUE_S: synchronous queue
568 = QUEUE_A0: asynchronous queue
573 the transmit complete interrupt of a queue,
582 void enable_tx_irq(struct s_smc *smc, u_short queue)
583 /* u_short queue; 0 = synchronous queue, 1 = asynchronous queue 0 */
589 if (queue == 0) {
592 if (queue == 1) {
600 void disable_tx_irq(smc, queue)
602 u_short queue ;
606 interrupt of the queue
608 Para queue = QUEUE_S: synchronous queue
609 = QUEUE_A0: asynchronous queue
617 void disable_tx_irq(struct s_smc *smc, u_short queue)
618 /* u_short queue; 0 = synchronous queue, 1 = asynchronous queue 0 */
624 if (queue == 0) {
627 if (queue == 1) {
650 llc_restart_tx(smc) ; /* TX queue */
669 * mac2_irq: status bits for the receive queue 1, and ring status
796 * mac3_irq: receive queue 2 bits and address detection bits
809 if (code_s3u & FM_SRPERRQ2) { /* parity error receive queue 2 */
812 if (code_s3u & FM_SRPERRQ1) { /* parity error receive queue 2 */
958 /* Auto unlock receice threshold for receive queue 1 and 2 */
1371 rx queue 1 | RX_FIFO_SPACE | RX_LARGE_FIFO| ------------- * 63,75 kB
1375 rx queue 2 | 0 kB | RX_SMALL_FIFO| ------------- * 63,75 kB
1415 queue | | TX_MEDIUM_FIFO | TX_LARGE_FIFO
1418 queue | TX_FIFO_SPACE| TX_MEDIUM_FIFO | TX_SMALL_FIFO
1477 * bandwidth becomes available but no synchronous queue is