Lines Matching refs:rp
521 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
523 void __iomem *ioaddr = rp->base;
534 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
539 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
541 rhine_wait_bit(rp, reg, mask, false);
544 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
546 rhine_wait_bit(rp, reg, mask, true);
549 static u32 rhine_get_events(struct rhine_private *rp)
551 void __iomem *ioaddr = rp->base;
556 if (rp->quirks & rqStatusWBRace)
561 static void rhine_ack_events(struct rhine_private *rp, u32 mask)
563 void __iomem *ioaddr = rp->base;
565 if (rp->quirks & rqStatusWBRace)
576 struct rhine_private *rp = netdev_priv(dev);
577 void __iomem *ioaddr = rp->base;
580 if (rp->quirks & rqWOL) {
590 if (rp->quirks & rq6patterns)
595 if (rp->quirks & rq6patterns)
600 if (rp->quirks & rq6patterns)
632 struct rhine_private *rp = netdev_priv(dev);
633 void __iomem *ioaddr = rp->base;
643 if (rp->quirks & rqForceReset)
647 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
651 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
702 struct rhine_private *rp = netdev_priv(dev);
703 void __iomem *ioaddr = rp->base;
719 enable_mmio(pioaddr, rp->quirks);
722 if (rp->quirks & rqWOL)
730 struct rhine_private *rp = netdev_priv(dev);
731 const int irq = rp->irq;
739 static void rhine_kick_tx_threshold(struct rhine_private *rp)
741 if (rp->tx_thresh < 0xe0) {
742 void __iomem *ioaddr = rp->base;
744 rp->tx_thresh += 0x20;
745 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
749 static void rhine_tx_err(struct rhine_private *rp, u32 status)
751 struct net_device *dev = rp->dev;
754 netif_info(rp, tx_err, dev,
759 rhine_kick_tx_threshold(rp);
760 netif_info(rp, tx_err ,dev, "Transmitter underrun, "
761 "Tx threshold now %02x\n", rp->tx_thresh);
765 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
769 rhine_kick_tx_threshold(rp);
770 netif_info(rp, tx_err, dev, "Unspecified error. "
771 "Tx threshold now %02x\n", rp->tx_thresh);
777 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
779 void __iomem *ioaddr = rp->base;
780 struct net_device_stats *stats = &rp->dev->stats;
818 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
819 struct net_device *dev = rp->dev;
820 void __iomem *ioaddr = rp->base;
825 status = rhine_get_events(rp);
826 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
834 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
836 netif_warn(rp, tx_err, dev, "Tx still on\n");
842 rhine_tx_err(rp, status);
846 spin_lock(&rp->lock);
847 rhine_update_rx_crc_and_missed_errord(rp);
848 spin_unlock(&rp->lock);
853 schedule_work(&rp->slow_event_task);
865 struct rhine_private *rp = netdev_priv(dev);
871 if (rp->quirks & rqRhineI)
900 struct rhine_private *rp;
918 rp = netdev_priv(dev);
919 rp->dev = dev;
920 rp->quirks = quirks;
921 rp->pioaddr = pioaddr;
922 rp->base = ioaddr;
923 rp->irq = irq;
924 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
926 phy_id = rp->quirks & rqIntPHY ? 1 : 0;
928 u64_stats_init(&rp->tx_stats.syncp);
929 u64_stats_init(&rp->rx_stats.syncp);
950 spin_lock_init(&rp->lock);
951 mutex_init(&rp->task_lock);
952 INIT_WORK(&rp->reset_task, rhine_reset_task);
953 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
955 rp->mii_if.dev = dev;
956 rp->mii_if.mdio_read = mdio_read;
957 rp->mii_if.mdio_write = mdio_write;
958 rp->mii_if.phy_id_mask = 0x1f;
959 rp->mii_if.reg_num_mask = 0x1f;
966 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
968 if (rp->quirks & rqRhineI)
971 if (rp->quirks & rqMgmt)
981 if (rp->quirks & rqRhineI)
983 else if (rp->quirks & rqStatusWBRace)
985 else if (rp->quirks & rqMgmt)
991 name, ioaddr, dev->dev_addr, rp->irq);
1001 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
1005 mii_status, rp->mii_if.advertising,
1016 rp->mii_if.phy_id = phy_id;
1018 netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
1143 struct rhine_private *rp = netdev_priv(dev);
1157 if (rp->quirks & rqRhineI) {
1158 rp->tx_bufs = dma_alloc_coherent(hwdev,
1160 &rp->tx_bufs_dma,
1162 if (rp->tx_bufs == NULL) {
1171 rp->rx_ring = ring;
1172 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
1173 rp->rx_ring_dma = ring_dma;
1174 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
1181 struct rhine_private *rp = netdev_priv(dev);
1187 rp->rx_ring, rp->rx_ring_dma);
1188 rp->tx_ring = NULL;
1190 if (rp->tx_bufs)
1192 rp->tx_bufs, rp->tx_bufs_dma);
1194 rp->tx_bufs = NULL;
1206 struct rhine_private *rp = netdev_priv(dev);
1208 const int size = rp->rx_buf_sz;
1216 netif_err(rp, drv, dev, "Rx DMA mapping failure\n");
1224 static void rhine_reset_rbufs(struct rhine_private *rp)
1228 rp->cur_rx = 0;
1231 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1234 static inline void rhine_skb_dma_nic_store(struct rhine_private *rp,
1237 rp->rx_skbuff_dma[entry] = sd->dma;
1238 rp->rx_skbuff[entry] = sd->skb;
1240 rp->rx_ring[entry].addr = cpu_to_le32(sd->dma);
1248 struct rhine_private *rp = netdev_priv(dev);
1252 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1253 next = rp->rx_ring_dma;
1257 rp->rx_ring[i].rx_status = 0;
1258 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1260 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1261 rp->rx_skbuff[i] = NULL;
1264 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1276 rhine_skb_dma_nic_store(rp, &sd, i);
1279 rhine_reset_rbufs(rp);
1286 struct rhine_private *rp = netdev_priv(dev);
1292 rp->rx_ring[i].rx_status = 0;
1293 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1294 if (rp->rx_skbuff[i]) {
1296 rp->rx_skbuff_dma[i],
1297 rp->rx_buf_sz, DMA_FROM_DEVICE);
1298 dev_kfree_skb(rp->rx_skbuff[i]);
1300 rp->rx_skbuff[i] = NULL;
1306 struct rhine_private *rp = netdev_priv(dev);
1310 rp->dirty_tx = rp->cur_tx = 0;
1311 next = rp->tx_ring_dma;
1313 rp->tx_skbuff[i] = NULL;
1314 rp->tx_ring[i].tx_status = 0;
1315 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1317 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1318 if (rp->quirks & rqRhineI)
1319 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1321 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1328 struct rhine_private *rp = netdev_priv(dev);
1333 rp->tx_ring[i].tx_status = 0;
1334 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1335 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1336 if (rp->tx_skbuff[i]) {
1337 if (rp->tx_skbuff_dma[i]) {
1339 rp->tx_skbuff_dma[i],
1340 rp->tx_skbuff[i]->len,
1343 dev_kfree_skb(rp->tx_skbuff[i]);
1345 rp->tx_skbuff[i] = NULL;
1346 rp->tx_buf[i] = NULL;
1352 struct rhine_private *rp = netdev_priv(dev);
1353 void __iomem *ioaddr = rp->base;
1355 if (!rp->mii_if.force_media)
1356 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
1358 if (rp->mii_if.full_duplex)
1365 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1366 rp->mii_if.force_media, netif_carrier_ok(dev));
1373 struct rhine_private *rp = netdev_priv(dev);
1383 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1493 struct rhine_private *rp = netdev_priv(dev);
1494 void __iomem *ioaddr = rp->base;
1513 struct rhine_private *rp = netdev_priv(dev);
1514 void __iomem *ioaddr = rp->base;
1519 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1530 struct rhine_private *rp = netdev_priv(dev);
1532 spin_lock_bh(&rp->lock);
1533 set_bit(vid, rp->active_vlans);
1535 spin_unlock_bh(&rp->lock);
1541 struct rhine_private *rp = netdev_priv(dev);
1543 spin_lock_bh(&rp->lock);
1544 clear_bit(vid, rp->active_vlans);
1546 spin_unlock_bh(&rp->lock);
1552 struct rhine_private *rp = netdev_priv(dev);
1553 void __iomem *ioaddr = rp->base;
1563 rp->tx_thresh = 0x20;
1564 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1566 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1567 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1571 if (rp->quirks & rqMgmt)
1574 napi_enable(&rp->napi);
1584 static void rhine_enable_linkmon(struct rhine_private *rp)
1586 void __iomem *ioaddr = rp->base;
1592 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1598 static void rhine_disable_linkmon(struct rhine_private *rp)
1600 void __iomem *ioaddr = rp->base;
1604 if (rp->quirks & rqRhineI) {
1613 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1619 rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
1626 struct rhine_private *rp = netdev_priv(dev);
1627 void __iomem *ioaddr = rp->base;
1630 rhine_disable_linkmon(rp);
1636 rhine_wait_bit_low(rp, MIICmd, 0x40);
1639 rhine_enable_linkmon(rp);
1645 struct rhine_private *rp = netdev_priv(dev);
1646 void __iomem *ioaddr = rp->base;
1648 rhine_disable_linkmon(rp);
1655 rhine_wait_bit_low(rp, MIICmd, 0x20);
1657 rhine_enable_linkmon(rp);
1660 static void rhine_task_disable(struct rhine_private *rp)
1662 mutex_lock(&rp->task_lock);
1663 rp->task_enable = false;
1664 mutex_unlock(&rp->task_lock);
1666 cancel_work_sync(&rp->slow_event_task);
1667 cancel_work_sync(&rp->reset_task);
1670 static void rhine_task_enable(struct rhine_private *rp)
1672 mutex_lock(&rp->task_lock);
1673 rp->task_enable = true;
1674 mutex_unlock(&rp->task_lock);
1679 struct rhine_private *rp = netdev_priv(dev);
1680 void __iomem *ioaddr = rp->base;
1683 rc = request_irq(rp->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev);
1687 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->irq);
1698 enable_mmio(rp->pioaddr, rp->quirks);
1701 rhine_task_enable(rp);
1704 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
1706 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1716 free_irq(rp->irq, dev);
1722 struct rhine_private *rp = container_of(work, struct rhine_private,
1724 struct net_device *dev = rp->dev;
1726 mutex_lock(&rp->task_lock);
1728 if (!rp->task_enable)
1731 napi_disable(&rp->napi);
1733 spin_lock_bh(&rp->lock);
1739 rhine_reset_rbufs(rp);
1745 spin_unlock_bh(&rp->lock);
1752 mutex_unlock(&rp->task_lock);
1757 struct rhine_private *rp = netdev_priv(dev);
1758 void __iomem *ioaddr = rp->base;
1762 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1764 schedule_work(&rp->reset_task);
1767 static inline bool rhine_tx_queue_full(struct rhine_private *rp)
1769 return (rp->cur_tx - rp->dirty_tx) >= TX_QUEUE_LEN;
1775 struct rhine_private *rp = netdev_priv(dev);
1777 void __iomem *ioaddr = rp->base;
1784 entry = rp->cur_tx % TX_RING_SIZE;
1789 rp->tx_skbuff[entry] = skb;
1791 if ((rp->quirks & rqRhineI) &&
1797 rp->tx_skbuff[entry] = NULL;
1803 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1805 memset(rp->tx_buf[entry] + skb->len, 0,
1807 rp->tx_skbuff_dma[entry] = 0;
1808 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1809 (rp->tx_buf[entry] -
1810 rp->tx_bufs));
1812 rp->tx_skbuff_dma[entry] =
1815 if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) {
1817 rp->tx_skbuff_dma[entry] = 0;
1821 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1824 rp->tx_ring[entry].desc_length =
1833 rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16);
1835 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1838 rp->tx_ring[entry].tx_status = 0;
1843 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1846 rp->cur_tx++;
1866 if (rhine_tx_queue_full(rp)) {
1870 if (!rhine_tx_queue_full(rp))
1874 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
1875 rp->cur_tx - 1, entry);
1880 static void rhine_irq_disable(struct rhine_private *rp)
1882 iowrite16(0x0000, rp->base + IntrEnable);
1890 struct rhine_private *rp = netdev_priv(dev);
1894 status = rhine_get_events(rp);
1896 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
1901 rhine_irq_disable(rp);
1902 napi_schedule(&rp->napi);
1906 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
1917 struct rhine_private *rp = netdev_priv(dev);
1920 unsigned int dirty_tx = rp->dirty_tx;
1931 cur_tx = rp->cur_tx;
1935 u32 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1937 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
1941 skb = rp->tx_skbuff[entry];
1943 netif_dbg(rp, tx_done, dev,
1954 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1957 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1962 if (rp->quirks & rqRhineI)
1966 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
1969 u64_stats_update_begin(&rp->tx_stats.syncp);
1970 rp->tx_stats.bytes += skb->len;
1971 rp->tx_stats.packets++;
1972 u64_stats_update_end(&rp->tx_stats.syncp);
1975 if (rp->tx_skbuff_dma[entry]) {
1977 rp->tx_skbuff_dma[entry],
1984 rp->tx_skbuff[entry] = NULL;
1988 rp->dirty_tx = dirty_tx;
1995 if (!rhine_tx_queue_full(rp) && netif_queue_stopped(dev)) {
1999 if (rhine_tx_queue_full(rp))
2034 struct rhine_private *rp = netdev_priv(dev);
2036 int entry = rp->cur_rx % RX_RING_SIZE;
2039 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
2040 entry, le32_to_cpu(rp->rx_ring[entry].rx_status));
2044 struct rx_desc *desc = rp->rx_ring + entry;
2051 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
2064 netif_dbg(rp, rx_err, dev,
2076 spin_lock(&rp->lock);
2078 spin_unlock(&rp->lock);
2094 rp->rx_skbuff_dma[entry],
2095 rp->rx_buf_sz,
2099 rp->rx_skbuff[entry]->data,
2103 rp->rx_skbuff_dma[entry],
2104 rp->rx_buf_sz,
2112 skb = rp->rx_skbuff[entry];
2115 rp->rx_skbuff_dma[entry],
2116 rp->rx_buf_sz,
2118 rhine_skb_dma_nic_store(rp, &sd, entry);
2129 u64_stats_update_begin(&rp->rx_stats.syncp);
2130 rp->rx_stats.bytes += pkt_len;
2131 rp->rx_stats.packets++;
2132 u64_stats_update_end(&rp->rx_stats.syncp);
2136 entry = (++rp->cur_rx) % RX_RING_SIZE;
2147 struct rhine_private *rp = netdev_priv(dev);
2148 void __iomem *ioaddr = rp->base;
2149 int entry = rp->dirty_tx % TX_RING_SIZE;
2156 intr_status = rhine_get_events(rp);
2161 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
2167 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
2177 netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
2185 struct rhine_private *rp =
2187 struct net_device *dev = rp->dev;
2190 mutex_lock(&rp->task_lock);
2192 if (!rp->task_enable)
2195 intr_status = rhine_get_events(rp);
2196 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
2202 netif_warn(rp, hw, dev, "PCI error\n");
2204 iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable);
2207 mutex_unlock(&rp->task_lock);
2213 struct rhine_private *rp = netdev_priv(dev);
2216 spin_lock_bh(&rp->lock);
2217 rhine_update_rx_crc_and_missed_errord(rp);
2218 spin_unlock_bh(&rp->lock);
2223 start = u64_stats_fetch_begin_irq(&rp->rx_stats.syncp);
2224 stats->rx_packets = rp->rx_stats.packets;
2225 stats->rx_bytes = rp->rx_stats.bytes;
2226 } while (u64_stats_fetch_retry_irq(&rp->rx_stats.syncp, start));
2229 start = u64_stats_fetch_begin_irq(&rp->tx_stats.syncp);
2230 stats->tx_packets = rp->tx_stats.packets;
2231 stats->tx_bytes = rp->tx_stats.bytes;
2232 } while (u64_stats_fetch_retry_irq(&rp->tx_stats.syncp, start));
2237 struct rhine_private *rp = netdev_priv(dev);
2238 void __iomem *ioaddr = rp->base;
2252 } else if (rp->quirks & rqMgmt) {
2274 if (rp->quirks & rqMgmt) {
2294 struct rhine_private *rp = netdev_priv(dev);
2296 mutex_lock(&rp->task_lock);
2297 mii_ethtool_get_link_ksettings(&rp->mii_if, cmd);
2298 mutex_unlock(&rp->task_lock);
2306 struct rhine_private *rp = netdev_priv(dev);
2309 mutex_lock(&rp->task_lock);
2310 rc = mii_ethtool_set_link_ksettings(&rp->mii_if, cmd);
2311 rhine_set_carrier(&rp->mii_if);
2312 mutex_unlock(&rp->task_lock);
2319 struct rhine_private *rp = netdev_priv(dev);
2321 return mii_nway_restart(&rp->mii_if);
2326 struct rhine_private *rp = netdev_priv(dev);
2328 return mii_link_ok(&rp->mii_if);
2333 struct rhine_private *rp = netdev_priv(dev);
2335 return rp->msg_enable;
2340 struct rhine_private *rp = netdev_priv(dev);
2342 rp->msg_enable = value;
2347 struct rhine_private *rp = netdev_priv(dev);
2349 if (!(rp->quirks & rqWOL))
2352 spin_lock_irq(&rp->lock);
2355 wol->wolopts = rp->wolopts;
2356 spin_unlock_irq(&rp->lock);
2361 struct rhine_private *rp = netdev_priv(dev);
2365 if (!(rp->quirks & rqWOL))
2371 spin_lock_irq(&rp->lock);
2372 rp->wolopts = wol->wolopts;
2373 spin_unlock_irq(&rp->lock);
2392 struct rhine_private *rp = netdev_priv(dev);
2398 mutex_lock(&rp->task_lock);
2399 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2400 rhine_set_carrier(&rp->mii_if);
2401 mutex_unlock(&rp->task_lock);
2408 struct rhine_private *rp = netdev_priv(dev);
2409 void __iomem *ioaddr = rp->base;
2411 rhine_task_disable(rp);
2412 napi_disable(&rp->napi);
2415 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
2419 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2421 rhine_irq_disable(rp);
2426 free_irq(rp->irq, dev);
2438 struct rhine_private *rp = netdev_priv(dev);
2442 pci_iounmap(pdev, rp->base);
2452 struct rhine_private *rp = netdev_priv(dev);
2456 iounmap(rp->base);
2466 struct rhine_private *rp = netdev_priv(dev);
2467 void __iomem *ioaddr = rp->base;
2469 if (!(rp->quirks & rqWOL))
2475 if (rp->quirks & rq6patterns)
2478 spin_lock(&rp->lock);
2480 if (rp->wolopts & WAKE_MAGIC) {
2489 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2492 if (rp->wolopts & WAKE_PHY)
2495 if (rp->wolopts & WAKE_UCAST)
2498 if (rp->wolopts) {
2504 spin_unlock(&rp->lock);
2518 struct rhine_private *rp = netdev_priv(dev);
2523 rhine_task_disable(rp);
2524 rhine_irq_disable(rp);
2525 napi_disable(&rp->napi);
2538 struct rhine_private *rp = netdev_priv(dev);
2543 enable_mmio(rp->pioaddr, rp->quirks);
2547 rhine_reset_rbufs(rp);
2548 rhine_task_enable(rp);
2549 spin_lock_bh(&rp->lock);
2551 spin_unlock_bh(&rp->lock);