Lines Matching refs:tc_readl
379 #define tc_readl(addr) ioread32(addr)
511 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
516 return tc_readl(&tr->MD_Data) & 0xffff;
530 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
552 reg = tc_readl(&tr->MAC_Ctl);
574 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
730 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
735 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
737 data = tc_readl(&tr->PROM_Data);
1189 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1200 dev->name, tc_readl(&tr->Tx_Stat));
1433 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1445 (void)tc_readl(&tr->Int_Src); /* flush */
1633 status = tc_readl(&tr->Int_Src);
1648 status = tc_readl(&tr->Int_Src);
1655 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1857 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1871 saved_addr = tc_readl(&tr->CAM_Adr);
1879 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1893 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2028 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2050 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */