Lines Matching defs:tc_writel
380 #define tc_writel(d, addr) iowrite32(d, addr)
509 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
526 tc_writel(val, &tr->MD_Data);
527 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
554 tc_writel(reg, &tr->MAC_Ctl);
559 tc_writel(reg, &tr->MAC_Ctl);
561 tc_writel(reg, &tr->MAC_Ctl);
574 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
734 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
1188 tc_writel(0, &tr->Int_En);
1189 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1320 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1437 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1636 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1641 tc_writel(status & (Int_BLEx | Int_FDAEx),
1655 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1700 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1811 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1878 tc_writel(cam_index - 2, &tr->CAM_Adr);
1881 tc_writel(cam_data, &tr->CAM_Data);
1883 tc_writel(cam_index + 2, &tr->CAM_Adr);
1885 tc_writel(cam_data, &tr->CAM_Data);
1888 tc_writel(cam_index, &tr->CAM_Adr);
1890 tc_writel(cam_data, &tr->CAM_Data);
1892 tc_writel(cam_index + 4, &tr->CAM_Adr);
1895 tc_writel(cam_data, &tr->CAM_Data);
1898 tc_writel(saved_addr, &tr->CAM_Adr);
1923 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1928 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1934 tc_writel(0, &tr->CAM_Ctl);
1943 tc_writel(ena_bits, &tr->CAM_Ena);
1944 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1946 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1947 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2025 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2035 tc_writel(0, &tr->MAC_Ctl);
2038 tc_writel(0, &tr->DMA_Ctl);
2039 tc_writel(0, &tr->TxThrsh);
2040 tc_writel(0, &tr->TxPollCtr);
2041 tc_writel(0, &tr->RxFragSize);
2042 tc_writel(0, &tr->Int_En);
2043 tc_writel(0, &tr->FDA_Bas);
2044 tc_writel(0, &tr->FDA_Lim);
2045 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2046 tc_writel(0, &tr->CAM_Ctl);
2047 tc_writel(0, &tr->Tx_Ctl);
2048 tc_writel(0, &tr->Rx_Ctl);
2049 tc_writel(0, &tr->CAM_Ena);
2053 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2055 tc_writel(i, &tr->CAM_Adr);
2056 tc_writel(0, &tr->CAM_Data);
2058 tc_writel(0, &tr->DMA_Ctl);
2072 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2073 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2077 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2079 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2080 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2081 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2082 tc_writel(INT_EN_CMD, &tr->Int_En);
2085 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2086 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2093 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2094 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2103 tc_writel(txctl, &tr->Tx_Ctl);