Lines Matching defs:access
65 u32 access;
115 * In the worst case, we could be kicking off a user-access immediately
117 * so, our request could get deferred by one access cycle. We
118 * defensively allow for 4 access cycles.
176 /* wait until hardware is ready for another user access */
184 reg = readl(®s->user[0].access);
204 reg = readl(®s->user[0].access);
208 dev_err(data->dev, "timed out waiting for user access\n");
251 writel(reg, &data->regs->user[0].access);
259 reg = readl(&data->regs->user[0].access);
295 writel(reg, &data->regs->user[0].access);