Lines Matching defs:cpmac_write
144 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
271 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
284 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
300 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
317 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
320 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
323 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
324 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
347 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
348 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
360 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
489 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
502 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
575 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
586 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
618 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
620 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
623 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
624 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
626 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
627 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
628 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
629 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
630 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
642 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
643 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
645 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
647 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
649 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
651 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
652 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
653 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
656 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
657 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
658 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
659 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
660 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
661 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
662 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
663 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
664 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
666 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
668 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
670 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
729 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
764 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
787 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
792 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
1015 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1016 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1017 cpmac_write(priv->regs, CPMAC_MBP, 0);