Lines Matching refs:val
63 u32 val;
65 val = readl(common->cpsw_base + AM65_CPSW_REG_CTL);
68 val |= AM65_CPSW_CTL_EST_EN;
70 val &= ~AM65_CPSW_CTL_EST_EN;
72 writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
78 u32 val;
80 val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
82 val |= AM65_CPSW_PN_CTL_EST_PORT_EN;
84 val &= ~AM65_CPSW_PN_CTL_EST_PORT_EN;
86 writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
94 u32 val;
96 val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
98 val |= AM65_CPSW_PN_EST_BUFSEL;
100 val &= ~AM65_CPSW_PN_EST_BUFSEL;
102 writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
118 u32 val;
120 val = readl(port->port_base + AM65_CPSW_PN_REG_FIFO_STATUS);
121 *oper = !!(val & AM65_CPSW_PN_FST_EST_BUFACT);
123 val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
124 *admin = !!(val & AM65_CPSW_PN_EST_BUFSEL);
178 u32 val;
180 val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
181 val &= ~AM65_CPSW_PN_EST_ONEBUF;
182 writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);