Lines Matching refs:wptr
171 f->wptr = 0;
1107 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1115 f->m.wptr += sizeof(struct rxf_desc);
1116 delta = f->m.wptr - f->m.memsz;
1118 f->m.wptr = delta;
1126 /*TBD: to do - delayed rxf wptr like in txd */
1127 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1162 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1170 f->m.wptr += sizeof(struct rxf_desc);
1171 delta = f->m.wptr - f->m.memsz;
1173 f->m.wptr = delta;
1214 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1216 size = f->m.wptr - f->m.rptr;
1377 *pptr != db->wptr); /* or write pointer */
1393 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1403 __bdx_tx_db_ptr_next(db, &db->wptr);
1404 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1426 * avoid rptr == wptr which means db is empty
1433 d->wptr = d->start;
1482 db->wptr->len = skb_headlen(skb);
1483 db->wptr->addr.dma = dma_map_single(&priv->pdev->dev, skb->data,
1484 db->wptr->len, DMA_TO_DEVICE);
1485 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1486 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1487 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1497 db->wptr->len = skb_frag_size(frag);
1498 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1503 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1504 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1505 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1510 db->wptr->len = -txd_sizes[nr_frags].bytes;
1511 db->wptr->addr.skb = skb;
1574 fsize = f->m.rptr - f->m.wptr;
1611 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1612 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1644 f->m.wptr += txd_sizes[nr_frags].bytes;
1645 len = f->m.wptr - f->m.memsz;
1647 f->m.wptr = len;
1653 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1663 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1668 f->m.wptr & TXF_WPTR_WR_PTR);
1676 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1709 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1712 while (f->m.wptr != f->m.rptr) {
1733 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1745 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1770 while (db->rptr != db->wptr) {
1805 int i = f->m.memsz - f->m.wptr;
1811 memcpy(f->m.va + f->m.wptr, data, size);
1812 f->m.wptr += size;
1814 memcpy(f->m.va + f->m.wptr, data, i);
1815 f->m.wptr = size - i;
1816 memcpy(f->m.va, data + i, f->m.wptr);
1818 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1836 /* we substruct 8 because when fifo is full rptr == wptr