Lines Matching refs:regval
38 u32 regval;
40 regval = readl(pdata->mac_regs + MAC_RCR);
41 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
43 writel(regval, pdata->mac_regs + MAC_RCR);
50 u32 regval;
52 regval = readl(pdata->mac_regs + MAC_RCR);
53 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
55 writel(regval, pdata->mac_regs + MAC_RCR);
112 u32 regval;
114 regval = readl(pdata->mac_regs + MAC_VLANTR);
116 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS,
119 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS,
122 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS,
125 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS,
128 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
130 writel(regval, pdata->mac_regs + MAC_VLANTR);
137 u32 regval;
139 regval = readl(pdata->mac_regs + MAC_VLANTR);
140 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
142 writel(regval, pdata->mac_regs + MAC_VLANTR);
149 u32 regval;
151 regval = readl(pdata->mac_regs + MAC_PFR);
153 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
155 writel(regval, pdata->mac_regs + MAC_PFR);
157 regval = readl(pdata->mac_regs + MAC_VLANTR);
159 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS,
162 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS,
165 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS,
173 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS,
175 writel(regval, pdata->mac_regs + MAC_VLANTR);
182 u32 regval;
184 regval = readl(pdata->mac_regs + MAC_PFR);
186 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
188 writel(regval, pdata->mac_regs + MAC_PFR);
221 u32 regval;
234 regval = readl(pdata->mac_regs + MAC_VLANHTR);
236 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS,
238 writel(regval, pdata->mac_regs + MAC_VLANHTR);
247 u32 regval;
249 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
251 if (regval == val)
257 regval = readl(pdata->mac_regs + MAC_PFR);
258 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS,
260 writel(regval, pdata->mac_regs + MAC_PFR);
277 u32 regval;
279 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
281 if (regval == val)
287 regval = readl(pdata->mac_regs + MAC_PFR);
288 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS,
290 writel(regval, pdata->mac_regs + MAC_PFR);
375 u32 regval;
381 regval = readl(pdata->mac_regs + MAC_PFR);
382 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS,
384 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS,
386 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS,
388 writel(regval, pdata->mac_regs + MAC_PFR);
395 u32 regval;
399 regval = readl(pdata->mac_regs + MAC_RCR);
400 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS,
402 writel(regval, pdata->mac_regs + MAC_RCR);
415 u32 regval;
417 regval = readl(pdata->mac_regs + MAC_VLANIR);
419 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS,
421 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS,
423 writel(regval, pdata->mac_regs + MAC_VLANIR);
501 u32 regval;
509 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
510 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
512 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
517 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
518 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
521 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
525 regval = readl(pdata->mac_regs + MAC_TCR);
526 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
528 writel(regval, pdata->mac_regs + MAC_TCR);
535 u32 regval;
547 regval = readl(pdata->mac_regs + MAC_TCR);
548 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
550 writel(regval, pdata->mac_regs + MAC_TCR);
554 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
555 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
557 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
566 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
567 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
569 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
605 unsigned int regval, i;
613 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
614 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
616 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
620 regval = 0;
622 regval |= (0x02 << (i << 1));
623 writel(regval, pdata->mac_regs + MAC_RQC0R);
626 regval = readl(pdata->mac_regs + MAC_RCR);
627 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
629 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
631 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
633 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
635 writel(regval, pdata->mac_regs + MAC_RCR);
642 u32 regval;
645 regval = readl(pdata->mac_regs + MAC_RCR);
646 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
648 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
650 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
652 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
654 writel(regval, pdata->mac_regs + MAC_RCR);
669 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
670 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
672 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1191 unsigned int reg, regval;
1196 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1197 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
1199 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1207 regval = readl(pdata->mac_regs + reg);
1208 regval = XLGMAC_SET_REG_BITS(regval,
1212 writel(regval, pdata->mac_regs + reg);
1223 unsigned int reg, regval;
1228 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1229 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
1231 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1239 regval = readl(pdata->mac_regs + reg);
1242 regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS,
1245 regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS,
1248 writel(regval, pdata->mac_regs + reg);
1258 u32 regval;
1260 regval = readl(pdata->mac_regs + MAC_RFCR);
1261 regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
1263 writel(regval, pdata->mac_regs + MAC_RFCR);
1270 u32 regval;
1272 regval = readl(pdata->mac_regs + MAC_RFCR);
1273 regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
1275 writel(regval, pdata->mac_regs + MAC_RFCR);
1304 u32 regval;
1311 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
1312 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS,
1315 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
1330 u32 regval;
1333 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1334 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS,
1336 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1343 u32 regval;
1346 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1347 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS,
1349 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1362 u32 regval;
1369 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1370 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS,
1373 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1381 u32 regval;
1389 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1390 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS,
1392 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1401 u32 regval;
1408 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
1409 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS,
1411 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
1414 regval = readl(pdata->mac_regs + MAC_RCR);
1415 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS,
1418 writel(regval, pdata->mac_regs + MAC_RCR);
1461 u32 regval;
1464 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1465 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS,
1467 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1476 u32 regval;
1479 regval = readl(pdata->mac_regs + MTL_OMR);
1480 regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS,
1482 writel(regval, pdata->mac_regs + MTL_OMR);
1486 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
1487 regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS,
1489 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
1491 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
1492 regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS,
1494 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
1498 regval = readl(pdata->mac_regs + MTL_OMR);
1499 regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS,
1501 writel(regval, pdata->mac_regs + MTL_OMR);
1508 unsigned int reg, regval;
1522 regval = readl(XLGMAC_MTL_REG(pdata, queue,
1524 regval = XLGMAC_SET_REG_BITS(regval,
1528 writel(regval, XLGMAC_MTL_REG(pdata, queue,
1536 regval = readl(XLGMAC_MTL_REG(pdata, queue,
1538 regval = XLGMAC_SET_REG_BITS(regval,
1542 writel(regval, XLGMAC_MTL_REG(pdata, queue,
1555 regval = 0;
1572 regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
1577 writel(regval, pdata->mac_regs + reg);
1579 regval = 0;
1586 regval = readl(pdata->mac_regs + reg);
1587 regval |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH |
1589 writel(regval, pdata->mac_regs + reg);
1592 regval = readl(pdata->mac_regs + reg);
1593 regval |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH |
1595 writel(regval, pdata->mac_regs + reg);
1598 regval = readl(pdata->mac_regs + reg);
1599 regval |= (MTL_RQDCM2R_Q8MDMACH | MTL_RQDCM2R_Q9MDMACH |
1601 writel(regval, pdata->mac_regs + reg);
1634 u32 regval;
1641 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1642 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS,
1644 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1656 u32 regval;
1663 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1664 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS,
1666 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1677 u32 regval;
1680 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
1682 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS,
1685 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS,
1687 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
1695 u32 regval;
1698 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1699 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS,
1701 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1711 u32 regval;
1714 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1715 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS,
1717 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1727 u32 regval;
1730 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1731 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS,
1733 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1743 u32 regval;
1750 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1751 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS,
1754 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1764 u32 regval;
1768 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
1769 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS,
1772 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
1780 u32 regval;
1782 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));
1783 regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,
1785 return regval;
1792 u32 regval;
1799 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1800 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,
1803 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1811 u32 regval;
1813 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR));
1814 regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,
1816 return regval;
1823 u32 regval;
1830 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1831 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,
1834 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
2127 u32 regval;
2130 regval = readl(pdata->mac_regs + MMC_CR);
2131 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
2133 writel(regval, pdata->mac_regs + MMC_CR);
2259 regval = readl(pdata->mac_regs + MMC_CR);
2260 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
2262 writel(regval, pdata->mac_regs + MMC_CR);
2267 u32 regval;
2269 regval = readl(pdata->mac_regs + MMC_CR);
2271 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS,
2274 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS,
2276 writel(regval, pdata->mac_regs + MMC_CR);
2284 u32 regval;
2288 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
2290 if (regval) {
2297 regval = readl(pdata->mac_regs + MAC_RSSAR);
2298 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS,
2300 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS,
2302 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS,
2304 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS,
2306 writel(regval, pdata->mac_regs + MAC_RSSAR);
2310 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
2313 if (!regval)
2386 u32 regval;
2406 regval = readl(pdata->mac_regs + MAC_RSSCR);
2407 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
2409 writel(regval, pdata->mac_regs + MAC_RSSCR);
2416 u32 regval;
2421 regval = readl(pdata->mac_regs + MAC_RSSCR);
2422 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
2424 writel(regval, pdata->mac_regs + MAC_RSSCR);
2530 u32 regval;
2539 regval = readl(pdata->mac_regs + MMC_RIER);
2540 regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS,
2542 writel(regval, pdata->mac_regs + MMC_RIER);
2543 regval = readl(pdata->mac_regs + MMC_TIER);
2544 regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS,
2546 writel(regval, pdata->mac_regs + MMC_TIER);
2551 u32 regval;
2553 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2555 if (regval == 0x1)
2558 regval = readl(pdata->mac_regs + MAC_TCR);
2559 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2561 writel(regval, pdata->mac_regs + MAC_TCR);
2568 u32 regval;
2570 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2572 if (regval == 0)
2575 regval = readl(pdata->mac_regs + MAC_TCR);
2576 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2578 writel(regval, pdata->mac_regs + MAC_TCR);
2585 u32 regval;
2587 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2589 if (regval == 0x2)
2592 regval = readl(pdata->mac_regs + MAC_TCR);
2593 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2595 writel(regval, pdata->mac_regs + MAC_TCR);
2602 u32 regval;
2604 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2606 if (regval == 0x3)
2609 regval = readl(pdata->mac_regs + MAC_TCR);
2610 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2612 writel(regval, pdata->mac_regs + MAC_TCR);
2946 u32 regval;
2949 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2950 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,
2952 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2958 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2959 regval = XLGMAC_GET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,
2961 while (--count && regval)
2973 u32 regval;
2975 regval = readl(pdata->mac_regs + DMA_SBMR);
2977 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS,
2980 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS,
2982 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS,
2984 writel(regval, pdata->mac_regs + DMA_SBMR);
3044 u32 regval;
3047 regval = readl(pdata->mac_regs + DMA_MR);
3048 regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS,
3050 writel(regval, pdata->mac_regs + DMA_MR);