Lines Matching refs:hp
110 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
118 tlp->tx_new = hp->tx_new;
119 tlp->tx_old = hp->tx_old;
138 static __inline__ void tx_dump_ring(struct happy_meal *hp)
140 struct hmeal_init_block *hb = hp->happy_block;
154 #define tx_add_log(hp, a, s) do { } while(0)
156 #define tx_dump_ring(hp) do { } while(0)
304 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
321 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
323 hme_write32(hp, tregs + TCVR_BBDATA, bit);
324 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
329 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
333 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
335 ret = hme_read32(hp, tregs + TCVR_CFG);
345 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
351 retval = hme_read32(hp, tregs + TCVR_CFG);
356 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
363 static int happy_meal_bb_read(struct happy_meal *hp,
373 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
377 BB_PUT_BIT(hp, tregs, 1);
380 BB_PUT_BIT(hp, tregs, 0);
381 BB_PUT_BIT(hp, tregs, 1);
382 BB_PUT_BIT(hp, tregs, 1);
383 BB_PUT_BIT(hp, tregs, 0);
386 tmp = hp->paddr & 0xff;
388 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
393 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
396 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
399 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
401 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
402 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
404 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
409 static void happy_meal_bb_write(struct happy_meal *hp,
419 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
423 BB_PUT_BIT(hp, tregs, 1);
426 BB_PUT_BIT(hp, tregs, 0);
427 BB_PUT_BIT(hp, tregs, 1);
428 BB_PUT_BIT(hp, tregs, 0);
429 BB_PUT_BIT(hp, tregs, 1);
432 tmp = (hp->paddr & 0xff);
434 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
439 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
442 BB_PUT_BIT(hp, tregs, 1);
443 BB_PUT_BIT(hp, tregs, 0);
446 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
449 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
454 static int happy_meal_tcvr_read(struct happy_meal *hp,
461 if (hp->tcvr_type == none) {
466 if (!(hp->happy_flags & HFLAG_FENABLE)) {
468 return happy_meal_bb_read(hp, tregs, reg);
471 hme_write32(hp, tregs + TCVR_FRAME,
472 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
473 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
479 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
486 static void happy_meal_tcvr_write(struct happy_meal *hp,
495 if (!(hp->happy_flags & HFLAG_FENABLE)) {
496 happy_meal_bb_write(hp, tregs, reg, value);
501 hme_write32(hp, tregs + TCVR_FRAME,
502 (FRAME_WRITE | (hp->paddr << 23) |
504 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
546 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
548 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
553 if (hp->sw_bmcr & BMCR_FULLDPLX) {
554 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
555 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
560 if (hp->sw_bmcr & BMCR_SPEED100) {
561 hp->sw_bmcr &= ~(BMCR_SPEED100);
562 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
570 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
572 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
573 if (hp->tcvr_type == external)
578 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
579 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
580 if (hp->sw_lpa & LPA_100FULL)
585 if (hp->sw_lpa & LPA_10FULL)
592 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
594 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
595 if (hp->tcvr_type == external)
600 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
601 if (hp->sw_bmcr & BMCR_SPEED100)
605 if (hp->sw_bmcr & BMCR_FULLDPLX)
611 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
618 if (hp->timer_state == arbwait) {
619 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
620 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
622 if (hp->sw_lpa & LPA_100FULL)
624 else if (hp->sw_lpa & LPA_100HALF)
626 else if (hp->sw_lpa & LPA_10FULL)
632 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
633 if (hp->sw_bmcr & BMCR_FULLDPLX)
647 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
648 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
650 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
653 hp->happy_flags |= HFLAG_FULL;
654 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
655 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
658 hp->happy_flags &= ~(HFLAG_FULL);
659 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
660 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
663 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
664 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
671 static int happy_meal_init(struct happy_meal *hp);
673 static int is_lucent_phy(struct happy_meal *hp)
675 void __iomem *tregs = hp->tcvregs;
679 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
680 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
690 struct happy_meal *hp = from_timer(hp, t, happy_timer);
691 void __iomem *tregs = hp->tcvregs;
694 spin_lock_irq(&hp->happy_lock);
696 hp->timer_ticks++;
697 switch(hp->timer_state) {
702 if (hp->timer_ticks >= 10) {
705 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
707 hp->dev->name);
708 hp->sw_bmcr = BMCR_SPEED100;
709 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
711 if (!is_lucent_phy(hp)) {
716 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
717 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
718 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
720 hp->timer_state = ltrywait;
721 hp->timer_ticks = 0;
725 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
726 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
730 ret = set_happy_link_modes(hp, tregs);
742 hp->timer_state = lupwait;
756 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
757 if (hp->sw_bmsr & BMSR_LSTATUS) {
761 display_link_mode(hp, tregs);
762 hp->timer_state = asleep;
765 if (hp->timer_ticks >= 10) {
767 "not completely up.\n", hp->dev->name);
768 hp->timer_ticks = 0;
782 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
783 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
784 if (hp->timer_ticks == 1) {
785 if (!is_lucent_phy(hp)) {
789 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
790 happy_meal_tcvr_write(hp, tregs,
791 DP83840_CSCONFIG, hp->sw_csconfig);
796 if (hp->timer_ticks == 2) {
797 if (!is_lucent_phy(hp)) {
798 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
799 happy_meal_tcvr_write(hp, tregs,
800 DP83840_CSCONFIG, hp->sw_csconfig);
805 if (hp->sw_bmsr & BMSR_LSTATUS) {
807 display_forced_link_mode(hp, tregs);
808 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
809 hp->timer_state = asleep;
812 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
815 ret = try_next_permutation(hp, tregs);
823 hp->dev->name);
825 ret = happy_meal_init(hp);
829 "Happy Meal.\n", hp->dev->name);
833 if (!is_lucent_phy(hp)) {
834 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
836 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
837 happy_meal_tcvr_write(hp, tregs,
838 DP83840_CSCONFIG, hp->sw_csconfig);
840 hp->timer_ticks = 0;
852 hp->dev->name);
854 hp->timer_ticks = 0;
855 hp->timer_state = asleep; /* foo on you */
860 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
861 add_timer(&hp->happy_timer);
865 spin_unlock_irq(&hp->happy_lock);
871 /* hp->happy_lock must be held */
872 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
879 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
880 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
891 /* hp->happy_lock must be held */
892 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
899 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
900 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
913 /* hp->happy_lock must be held */
914 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
921 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
922 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
933 /* hp->happy_lock must be held */
934 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
936 struct net_device_stats *stats = &hp->dev->stats;
938 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
939 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
941 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
942 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
944 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
945 hme_write32(hp, bregs + BMAC_GLECTR, 0);
947 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
950 (hme_read32(hp, bregs + BMAC_EXCTR) +
951 hme_read32(hp, bregs + BMAC_LTCTR));
952 hme_write32(hp, bregs + BMAC_EXCTR, 0);
953 hme_write32(hp, bregs + BMAC_LTCTR, 0);
956 /* hp->happy_lock must be held */
957 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
962 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
970 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
974 hme_write32(hp, tregs + TCVR_CFG,
975 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
978 hp->happy_flags &= ~(HFLAG_POLL);
991 /* hp->happy_lock must be held */
992 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
997 tconfig = hme_read32(hp, tregs + TCVR_CFG);
999 if (hp->tcvr_type == external) {
1001 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1002 hp->tcvr_type = internal;
1003 hp->paddr = TCV_PADDR_ITX;
1005 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1007 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1013 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1014 hp->tcvr_type = external;
1015 hp->paddr = TCV_PADDR_ETX;
1019 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1021 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1023 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1029 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1030 hp->tcvr_type = internal;
1031 hp->paddr = TCV_PADDR_ITX;
1036 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1039 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1042 hp->sw_bmcr = result;
1054 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1055 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1056 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1057 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1060 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1061 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1065 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1077 if (!is_lucent_phy(hp)) {
1078 result = happy_meal_tcvr_read(hp, tregs,
1080 happy_meal_tcvr_write(hp, tregs,
1088 * hp->happy_lock must be held
1090 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1092 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1095 if (hp->happy_flags & HFLAG_POLL) {
1098 if (hp->tcvr_type == internal) {
1101 happy_meal_poll_stop(hp, tregs);
1102 hp->paddr = TCV_PADDR_ETX;
1103 hp->tcvr_type = external;
1107 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1110 if (hp->tcvr_type == external) {
1112 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1114 happy_meal_poll_stop(hp, tregs);
1115 hp->paddr = TCV_PADDR_ITX;
1116 hp->tcvr_type = internal;
1118 hme_write32(hp, tregs + TCVR_CFG,
1119 hme_read32(hp, tregs + TCVR_CFG) &
1128 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1133 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1134 hp->paddr = TCV_PADDR_ETX;
1135 hp->tcvr_type = external;
1139 hme_write32(hp, tregs + TCVR_CFG,
1141 hp->paddr = TCV_PADDR_ITX;
1142 hp->tcvr_type = internal;
1146 hp->tcvr_type = none; /* Grrr... */
1197 static void happy_meal_clean_rings(struct happy_meal *hp)
1202 if (hp->rx_skbs[i] != NULL) {
1203 struct sk_buff *skb = hp->rx_skbs[i];
1207 rxd = &hp->happy_block->happy_meal_rxd[i];
1208 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1209 dma_unmap_single(hp->dma_dev, dma_addr,
1212 hp->rx_skbs[i] = NULL;
1217 if (hp->tx_skbs[i] != NULL) {
1218 struct sk_buff *skb = hp->tx_skbs[i];
1223 hp->tx_skbs[i] = NULL;
1226 txd = &hp->happy_block->happy_meal_txd[i];
1227 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1229 dma_unmap_single(hp->dma_dev, dma_addr,
1230 (hme_read_desc32(hp, &txd->tx_flags)
1234 dma_unmap_page(hp->dma_dev, dma_addr,
1235 (hme_read_desc32(hp, &txd->tx_flags)
1248 /* hp->happy_lock must be held */
1249 static void happy_meal_init_rings(struct happy_meal *hp)
1251 struct hmeal_init_block *hb = hp->happy_block;
1255 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1259 happy_meal_clean_rings(hp);
1269 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1272 hp->rx_skbs[i] = skb;
1276 mapping = dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1278 if (dma_mapping_error(hp->dma_dev, mapping)) {
1280 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1283 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1291 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1296 /* hp->happy_lock must be held */
1298 happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1305 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1306 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1307 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1308 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1312 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1315 if (hp->sw_bmsr & BMSR_10HALF)
1316 hp->sw_advertise |= (ADVERTISE_10HALF);
1318 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1320 if (hp->sw_bmsr & BMSR_10FULL)
1321 hp->sw_advertise |= (ADVERTISE_10FULL);
1323 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1324 if (hp->sw_bmsr & BMSR_100HALF)
1325 hp->sw_advertise |= (ADVERTISE_100HALF);
1327 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1328 if (hp->sw_bmsr & BMSR_100FULL)
1329 hp->sw_advertise |= (ADVERTISE_100FULL);
1331 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1332 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1341 ASD(("%s: Advertising [ ", hp->dev->name));
1342 if (hp->sw_advertise & ADVERTISE_10HALF)
1344 if (hp->sw_advertise & ADVERTISE_10FULL)
1346 if (hp->sw_advertise & ADVERTISE_100HALF)
1348 if (hp->sw_advertise & ADVERTISE_100FULL)
1353 hp->sw_bmcr |= BMCR_ANENABLE;
1354 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1357 hp->sw_bmcr |= BMCR_ANRESTART;
1358 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1364 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1365 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1371 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1373 hp->dev->name);
1376 hp->timer_state = arbwait;
1389 hp->sw_bmcr = BMCR_SPEED100;
1392 hp->sw_bmcr = BMCR_SPEED100;
1394 hp->sw_bmcr = 0;
1396 hp->sw_bmcr |= BMCR_FULLDPLX;
1398 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1400 if (!is_lucent_phy(hp)) {
1405 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1407 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1408 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1409 hp->sw_csconfig);
1411 hp->timer_state = ltrywait;
1414 hp->timer_ticks = 0;
1415 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1416 add_timer(&hp->happy_timer);
1419 /* hp->happy_lock must be held */
1420 static int happy_meal_init(struct happy_meal *hp)
1422 void __iomem *gregs = hp->gregs;
1423 void __iomem *etxregs = hp->etxregs;
1424 void __iomem *erxregs = hp->erxregs;
1425 void __iomem *bregs = hp->bigmacregs;
1426 void __iomem *tregs = hp->tcvregs;
1428 unsigned char *e = &hp->dev->dev_addr[0];
1431 del_timer(&hp->happy_timer);
1434 hp->happy_flags));
1435 if (!(hp->happy_flags & HFLAG_INIT)) {
1437 hp->happy_flags |= HFLAG_INIT;
1438 happy_meal_get_counters(hp, bregs);
1443 happy_meal_poll_stop(hp, tregs);
1447 happy_meal_stop(hp, gregs);
1451 happy_meal_init_rings(hp);
1455 hme_read32(hp, tregs + TCVR_IMASK)));
1456 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1459 if (hp->happy_flags & HFLAG_FENABLE) {
1461 hme_read32(hp, tregs + TCVR_CFG)));
1462 hme_write32(hp, tregs + TCVR_CFG,
1463 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1466 hme_read32(hp, tregs + TCVR_CFG)));
1467 hme_write32(hp, tregs + TCVR_CFG,
1468 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1473 happy_meal_transceiver_check(hp, tregs);
1477 switch(hp->tcvr_type) {
1486 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1492 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1496 if (happy_meal_tcvr_reset(hp, tregs))
1501 happy_meal_tx_reset(hp, bregs);
1502 happy_meal_rx_reset(hp, bregs);
1506 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1507 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1508 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1514 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1516 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1517 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1518 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1521 if ((hp->dev->flags & IFF_ALLMULTI) ||
1522 (netdev_mc_count(hp->dev) > 64)) {
1523 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1524 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1525 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1526 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1527 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1533 netdev_for_each_mc_addr(ha, hp->dev) {
1538 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1539 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1540 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1541 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1543 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1544 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1545 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1546 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1551 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1552 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1553 hme_write32(hp, erxregs + ERX_RING,
1554 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1555 hme_write32(hp, etxregs + ETX_RING,
1556 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1563 if (hme_read32(hp, erxregs + ERX_RING) !=
1564 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1565 hme_write32(hp, erxregs + ERX_RING,
1566 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1571 hme_read32(hp, gregs + GREG_CFG)));
1575 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1577 if ((hp->happy_bursts & DMA_BURST64) &&
1578 ((hp->happy_flags & HFLAG_PCI) != 0
1590 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1591 struct platform_device *op = hp->happy_dev;
1594 hp->happy_bursts);
1601 hme_write32(hp, gregs + GREG_CFG, gcfg);
1602 } else if (hp->happy_bursts & DMA_BURST32) {
1604 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1605 } else if (hp->happy_bursts & DMA_BURST16) {
1607 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1610 hme_write32(hp, gregs + GREG_CFG, 0);
1616 hme_write32(hp, gregs + GREG_IMASK,
1622 hme_read32(hp, etxregs + ETX_RSIZE)));
1623 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1627 hme_read32(hp, etxregs + ETX_CFG)));
1628 hme_write32(hp, etxregs + ETX_CFG,
1629 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1637 hme_read32(hp, erxregs + ERX_CFG)));
1638 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1639 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1640 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1641 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1650 hme_read32(hp, bregs + BMAC_RXCFG)));
1652 if (hp->dev->flags & IFF_PROMISC)
1654 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1662 if (hp->happy_flags & HFLAG_FULL)
1668 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1671 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1677 if (hp->happy_flags & HFLAG_LANCE)
1681 if (hp->tcvr_type == external)
1685 hme_read32(hp, bregs + BMAC_XIFCFG)));
1686 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1690 hme_read32(hp, bregs + BMAC_TXCFG),
1691 hme_read32(hp, bregs + BMAC_RXCFG)));
1694 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1695 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1697 hme_write32(hp, bregs + BMAC_TXCFG,
1698 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1699 hme_write32(hp, bregs + BMAC_RXCFG,
1700 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1703 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1709 /* hp->happy_lock must be held */
1710 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1712 void __iomem *tregs = hp->tcvregs;
1713 void __iomem *bregs = hp->bigmacregs;
1714 void __iomem *gregs = hp->gregs;
1716 happy_meal_stop(hp, gregs);
1717 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1718 if (hp->happy_flags & HFLAG_FENABLE)
1719 hme_write32(hp, tregs + TCVR_CFG,
1720 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1722 hme_write32(hp, tregs + TCVR_CFG,
1723 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1724 happy_meal_transceiver_check(hp, tregs);
1725 switch(hp->tcvr_type) {
1729 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1732 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1735 if (happy_meal_tcvr_reset(hp, tregs))
1739 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1740 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1743 if (hp->sw_bmsr & BMSR_10HALF)
1744 hp->sw_advertise |= (ADVERTISE_10HALF);
1746 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1748 if (hp->sw_bmsr & BMSR_10FULL)
1749 hp->sw_advertise |= (ADVERTISE_10FULL);
1751 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1752 if (hp->sw_bmsr & BMSR_100HALF)
1753 hp->sw_advertise |= (ADVERTISE_100HALF);
1755 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1756 if (hp->sw_bmsr & BMSR_100FULL)
1757 hp->sw_advertise |= (ADVERTISE_100FULL);
1759 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1762 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1768 * hp->happy_lock must be held
1770 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1782 hp->dev->name, status);
1787 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1792 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1799 hp->dev->name);
1807 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1819 hp->dev->name);
1824 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1840 hp->dev->name);
1846 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1852 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1870 hp->dev->name,
1876 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1877 happy_meal_init(hp);
1883 /* hp->happy_lock must be held */
1884 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1886 void __iomem *tregs = hp->tcvregs;
1888 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1889 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1890 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1893 if (hp->sw_lpa & LPA_100FULL) {
1894 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1895 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1896 } else if (hp->sw_lpa & LPA_100HALF) {
1897 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1898 hp->sw_bmcr |= BMCR_SPEED100;
1899 } else if (hp->sw_lpa & LPA_10FULL) {
1900 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1901 hp->sw_bmcr |= BMCR_FULLDPLX;
1903 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1905 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1908 happy_meal_poll_stop(hp, tregs);
1917 /* hp->happy_lock must be held */
1918 static void happy_meal_tx(struct happy_meal *hp)
1920 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1922 struct net_device *dev = hp->dev;
1925 elem = hp->tx_old;
1927 while (elem != hp->tx_new) {
1934 flags = hme_read_desc32(hp, &this->tx_flags);
1937 skb = hp->tx_skbs[elem];
1943 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1947 hp->tx_skbs[elem] = NULL;
1951 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1952 dma_len = hme_read_desc32(hp, &this->tx_flags);
1956 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1958 dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1967 hp->tx_old = elem;
1971 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1988 * hp->happy_lock must be held
1990 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1992 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1994 int elem = hp->rx_new, drops = 0;
1999 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2003 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2021 hme_write_rxd(hp, this,
2026 skb = hp->rx_skbs[elem];
2038 mapping = dma_map_single(hp->dma_dev, new_skb->data,
2041 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
2047 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2048 hp->rx_skbs[elem] = new_skb;
2049 hme_write_rxd(hp, this,
2066 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE);
2068 dma_sync_single_for_device(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE);
2070 hme_write_rxd(hp, this,
2091 hp->rx_new = elem;
2093 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2100 struct happy_meal *hp = netdev_priv(dev);
2101 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2105 spin_lock(&hp->happy_lock);
2109 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2115 happy_meal_mif_interrupt(hp);
2120 happy_meal_tx(hp);
2125 happy_meal_rx(hp, dev);
2130 spin_unlock(&hp->happy_lock);
2143 struct happy_meal *hp = netdev_priv(dev);
2144 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2154 spin_lock(&hp->happy_lock);
2158 if (happy_meal_is_not_so_happy(hp, happy_status))
2164 happy_meal_mif_interrupt(hp);
2169 happy_meal_tx(hp);
2174 happy_meal_rx(hp, dev);
2178 spin_unlock(&hp->happy_lock);
2188 struct happy_meal *hp = netdev_priv(dev);
2196 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2197 res = request_irq(hp->irq, happy_meal_interrupt, IRQF_SHARED,
2202 hp->irq);
2210 spin_lock_irq(&hp->happy_lock);
2211 res = happy_meal_init(hp);
2212 spin_unlock_irq(&hp->happy_lock);
2214 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2215 free_irq(hp->irq, dev);
2221 struct happy_meal *hp = netdev_priv(dev);
2223 spin_lock_irq(&hp->happy_lock);
2224 happy_meal_stop(hp, hp->gregs);
2225 happy_meal_clean_rings(hp);
2228 del_timer(&hp->happy_timer);
2230 spin_unlock_irq(&hp->happy_lock);
2236 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2237 free_irq(hp->irq, dev);
2250 struct happy_meal *hp = netdev_priv(dev);
2255 hme_read32(hp, hp->gregs + GREG_STAT),
2256 hme_read32(hp, hp->etxregs + ETX_CFG),
2257 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2259 spin_lock_irq(&hp->happy_lock);
2260 happy_meal_init(hp);
2261 spin_unlock_irq(&hp->happy_lock);
2266 static void unmap_partial_tx_skb(struct happy_meal *hp, u32 first_mapping,
2269 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
2271 dma_unmap_single(hp->dma_dev, first_mapping, first_len, DMA_TO_DEVICE);
2278 addr = hme_read_desc32(hp, &this->tx_addr);
2279 len = hme_read_desc32(hp, &this->tx_flags);
2281 dma_unmap_page(hp->dma_dev, addr, len, DMA_TO_DEVICE);
2288 struct happy_meal *hp = netdev_priv(dev);
2302 spin_lock_irq(&hp->happy_lock);
2304 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2306 spin_unlock_irq(&hp->happy_lock);
2312 entry = hp->tx_new;
2314 hp->tx_skbs[entry] = skb;
2320 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2321 if (unlikely(dma_mapping_error(hp->dma_dev, mapping)))
2324 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2336 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2338 if (unlikely(dma_mapping_error(hp->dma_dev, first_mapping)))
2347 mapping = skb_frag_dma_map(hp->dma_dev, this_frag,
2349 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
2350 unmap_partial_tx_skb(hp, first_mapping, first_len,
2357 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2362 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2367 hp->tx_new = entry;
2369 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2373 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2375 spin_unlock_irq(&hp->happy_lock);
2377 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2381 hp->tx_skbs[hp->tx_new] = NULL;
2382 spin_unlock_irq(&hp->happy_lock);
2391 struct happy_meal *hp = netdev_priv(dev);
2393 spin_lock_irq(&hp->happy_lock);
2394 happy_meal_get_counters(hp, hp->bigmacregs);
2395 spin_unlock_irq(&hp->happy_lock);
2402 struct happy_meal *hp = netdev_priv(dev);
2403 void __iomem *bregs = hp->bigmacregs;
2407 spin_lock_irq(&hp->happy_lock);
2410 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2411 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2412 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2413 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2415 hme_write32(hp, bregs + BMAC_RXCFG,
2416 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2426 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2427 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2428 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2429 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2432 spin_unlock_irq(&hp->happy_lock);
2439 struct happy_meal *hp = netdev_priv(dev);
2453 spin_lock_irq(&hp->happy_lock);
2454 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2455 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2456 spin_unlock_irq(&hp->happy_lock);
2458 if (hp->sw_bmcr & BMCR_ANENABLE) {
2460 speed = ((hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2464 (hp->sw_lpa & (LPA_100FULL)) ?
2468 (hp->sw_lpa & (LPA_10FULL)) ?
2472 speed = (hp->sw_bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
2474 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2487 struct happy_meal *hp = netdev_priv(dev);
2501 spin_lock_irq(&hp->happy_lock);
2502 del_timer(&hp->happy_timer);
2503 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2504 spin_unlock_irq(&hp->happy_lock);
2511 struct happy_meal *hp = netdev_priv(dev);
2515 if (hp->happy_flags & HFLAG_PCI) {
2516 struct pci_dev *pdev = hp->happy_dev;
2522 struct platform_device *op = hp->happy_dev;
2534 struct happy_meal *hp = netdev_priv(dev);
2536 spin_lock_irq(&hp->happy_lock);
2537 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2538 spin_unlock_irq(&hp->happy_lock);
2540 return hp->sw_bmsr & BMSR_LSTATUS;
2685 struct happy_meal *hp;
2739 hp = netdev_priv(dev);
2741 hp->happy_dev = op;
2742 hp->dma_dev = &op->dev;
2744 spin_lock_init(&hp->happy_lock);
2748 hp->qfe_parent = qp;
2749 hp->qfe_ent = qfe_slot;
2753 hp->gregs = of_ioremap(&op->resource[0], 0,
2755 if (!hp->gregs) {
2760 hp->etxregs = of_ioremap(&op->resource[1], 0,
2762 if (!hp->etxregs) {
2767 hp->erxregs = of_ioremap(&op->resource[2], 0,
2769 if (!hp->erxregs) {
2774 hp->bigmacregs = of_ioremap(&op->resource[3], 0,
2776 if (!hp->bigmacregs) {
2781 hp->tcvregs = of_ioremap(&op->resource[4], 0,
2783 if (!hp->tcvregs) {
2788 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2789 if (hp->hm_revision == 0xff)
2790 hp->hm_revision = 0xa0;
2793 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2794 hp->happy_flags = HFLAG_20_21;
2795 else if (hp->hm_revision != 0xa0)
2796 hp->happy_flags = HFLAG_NOT_A0;
2799 hp->happy_flags |= HFLAG_QUATTRO;
2802 hp->happy_bursts = of_getintprop_default(sbus_dp,
2805 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2807 &hp->hblock_dvma,
2810 if (!hp->happy_block)
2814 hp->linkcheck = 0;
2817 hp->timer_state = asleep;
2818 hp->timer_ticks = 0;
2820 timer_setup(&hp->happy_timer, happy_meal_timer, 0);
2822 hp->dev = dev;
2831 hp->irq = op->archdata.irqs[0];
2835 hp->read_desc32 = sbus_hme_read_desc32;
2836 hp->write_txd = sbus_hme_write_txd;
2837 hp->write_rxd = sbus_hme_write_rxd;
2838 hp->read32 = sbus_hme_read32;
2839 hp->write32 = sbus_hme_write32;
2845 spin_lock_irq(&hp->happy_lock);
2846 happy_meal_set_initial_advertisement(hp);
2847 spin_unlock_irq(&hp->happy_lock);
2849 err = register_netdev(hp->dev);
2856 platform_set_drvdata(op, hp);
2870 dma_free_coherent(hp->dma_dev,
2872 hp->happy_block,
2873 hp->hblock_dvma);
2876 if (hp->gregs)
2877 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
2878 if (hp->etxregs)
2879 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
2880 if (hp->erxregs)
2881 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
2882 if (hp->bigmacregs)
2883 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
2884 if (hp->tcvregs)
2885 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
2990 struct happy_meal *hp;
3035 hp = netdev_priv(dev);
3037 hp->happy_dev = pdev;
3038 hp->dma_dev = &pdev->dev;
3040 spin_lock_init(&hp->happy_lock);
3043 hp->qfe_parent = qp;
3044 hp->qfe_ent = qfe_slot;
3092 hp->gregs = (hpreg_base + 0x0000UL);
3093 hp->etxregs = (hpreg_base + 0x2000UL);
3094 hp->erxregs = (hpreg_base + 0x4000UL);
3095 hp->bigmacregs = (hpreg_base + 0x6000UL);
3096 hp->tcvregs = (hpreg_base + 0x7000UL);
3099 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3100 if (hp->hm_revision == 0xff)
3101 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3104 hp->hm_revision = 0x20;
3108 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3109 hp->happy_flags = HFLAG_20_21;
3110 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3111 hp->happy_flags = HFLAG_NOT_A0;
3114 hp->happy_flags |= HFLAG_QUATTRO;
3117 hp->happy_flags |= HFLAG_PCI;
3121 hp->happy_bursts = DMA_BURSTBITS;
3124 hp->happy_block = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3125 &hp->hblock_dvma, GFP_KERNEL);
3127 if (!hp->happy_block)
3130 hp->linkcheck = 0;
3131 hp->timer_state = asleep;
3132 hp->timer_ticks = 0;
3134 timer_setup(&hp->happy_timer, happy_meal_timer, 0);
3136 hp->irq = pdev->irq;
3137 hp->dev = dev;
3148 hp->read_desc32 = pci_hme_read_desc32;
3149 hp->write_txd = pci_hme_write_txd;
3150 hp->write_rxd = pci_hme_write_rxd;
3151 hp->read32 = pci_hme_read32;
3152 hp->write32 = pci_hme_write32;
3158 spin_lock_irq(&hp->happy_lock);
3159 happy_meal_set_initial_advertisement(hp);
3160 spin_unlock_irq(&hp->happy_lock);
3162 err = register_netdev(hp->dev);
3169 pci_set_drvdata(pdev, hp);
3200 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3201 hp->happy_block, hp->hblock_dvma);
3204 iounmap(hp->gregs);
3221 struct happy_meal *hp = pci_get_drvdata(pdev);
3222 struct net_device *net_dev = hp->dev;
3226 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3227 hp->happy_block, hp->hblock_dvma);
3228 iounmap(hp->gregs);
3229 pci_release_regions(hp->happy_dev);
3291 struct happy_meal *hp = platform_get_drvdata(op);
3292 struct net_device *net_dev = hp->dev;
3298 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
3299 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
3300 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
3301 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
3302 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
3303 dma_free_coherent(hp->dma_dev,
3305 hp->happy_block,
3306 hp->hblock_dvma);